Zobrazeno 1 - 10
of 26
pro vyhledávání: '"William A. Starke"'
Publikováno v:
IEEE Micro. 41:7-14
The IBM POWER10 processor represents the 10th generation of the POWER family of enterprise computing engines. It is built on a balance of computation and bandwidth, delivered by powerful processing cores and intrachip interconnect, respectively. Mult
Autor:
Pradip Bose, William J. Starke, Christian Zoellin, Ramon Bertran, Satish Kumar Sadasivam, Alper Buyuktosunoglu, Silvia M. Müller, Matthias Pflanz, Robert K. Montoye, Michael Normand Goulet, John-David Wellman, Nagu Dhanwada, Dung Q. Nguyen, Marcy E. Byers, José E. Moreira, Balaram Sinharoy, Richard J. Eickemeyer, Christopher Gonzalez, Thompto Brian W, Andreas Wagner, Karthik Swaminathan, Hans M. Jacobson, Nandhini Chandramoorthy, Michael Stephen Floyd, Jeffrey A. Stuecheli, Rahul M. Rao
Publikováno v:
ISCA
We present the novel micro-architectural features, supported by an innovative and novel pre-silicon methodology in the design of POWER10. The resulting projected energy efficiency boost over POWER9 is 2.6x at core level (for SPECint) and up to 3x at
Autor:
Elaine R. Palmer, Kenneth Alan Goldman, Bharata Bhasker Rao, Hani Jamjoom, Lawrence Roy, Janani Janakirman, Brad Frey, Laurent Dufour, Ramachandra N. Pai, John M. Ludden, Cathy May, Guerney D. H. Hunt, Jeffrey A. Stuecheli, Wendel Glenn Voigt, Enriquillo Valdez, Sukadev Bhattiprolu, Mohit Kapur, Rick Boivie, William A. Starke, Paul Mackerras, Michael V. Le, Ryan P. Grimm
Publikováno v:
EuroSys
This paper presents Protected Execution Facility (PEF), a virtual machine-based Trusted Execution Environment (TEE) for confidential computing on Power ISA. PEF enables protected secure virtual machines (SVMs). Like other TEEs, PEF verifies the SVM p
Autor:
Thompto Brian W, William J. Starke
Publikováno v:
Hot Chips Symposium
Autor:
Craig B. Agricola, Haren Myneni, John J. Reilly, Ashutosh Mishra, Alper Buyuktosunoglu, William J. Starke, Bart Blaner, Bulent Abali, Bedri Sendir, Charlie Wang, Matthias Klein, Christian Jacobi
Publikováno v:
ISCA
Lossless data compression is highly desirable in enterprise and cloud environments for storage and memory cost savings and improved utilization I/O and network. While the value provided by compression is recognized, its application in practice is oft
Publikováno v:
IEEE Micro. 37:40-51
The IBM Power9 processor has an enhanced core and chip architecture that provides superior thread performance and higher throughput. The core and chip architectures are optimized for emerging workloads to support the needs of next-generation computin
Publikováno v:
Hot Chips Symposium
Autor:
Joachim Gerhard Clabes, Joshua Friedrich, J. Kahle, William J. Starke, Daniel M. Dreps, Victor Zyuban, James D. Warnock, Robert Alan Cargnoni, S. Weitzel, Scott A. Taylor, Phillip G. Williams, Jose Angel Paredes, Dieter Wendel, J. Pille, Gaurav Mittal, Saiful Islam, G Smith, J. A. Van Norstrand, Balaram Sinharoy, Phillip J. Restle, David A. Hrusecky, Sam Gat-Shang Chu, Ronald Nick Kalla, Jentje Leenstra
Publikováno v:
IEEE Journal of Solid-State Circuits. 46:145-161
This paper gives an overview of the latest member of the POWER™ processor family, POWER7™. Eight quad-threaded cores, operating at frequencies up to 4.14 GHz, are integrated together with two memory controllers and high speed system links on a 56
Autor:
James A. Marcella, Jeffrey A. Stuecheli, Brad W. Michael, Stephen J. Powell, John Steven Dodson, William J. Starke, Eric E. Retter
Publikováno v:
IBM Journal of Research and Development. 62:3:1-3:13
The IBM POWER9 processor chipset provides a variety of system memory architecture interfaces to enable highly differentiated system offerings: a high bandwidth, high capacity, highly reliable, buffered architecture; a compute-density-optimized direct
Autor:
C. Wollbrink, L. B. Arimilli, B. Allison, Bartholomew Blaner, Jeffrey A. Stuecheli, William J. Starke, J. D. Irish, Daniel M. Dreps
Publikováno v:
IBM Journal of Research and Development. 62:8:1-8:8
Open Coherent Accelerator Processor Interface (OpenCAPI) is a new industry-standard device interface that enables the development of host-agnostic devices that can coherently connect to any host platform that supports the OpenCAPI standard. This in t