Zobrazeno 1 - 10
of 47
pro vyhledávání: '"Wieslaw Kuzmicz"'
Autor:
Piotr Mierzwinski, Wieslaw Kuzmicz
Publikováno v:
Electronics; Volume 12; Issue 8; Pages: 1871
This paper summarizes the results of investigations of bipolar transistors made in VESTIC (Vertical Slit Transistor-based Integrated Circuits) technology. This technology was proposed by W. Maly as an alternative to classical bulk CMOS technology. Ho
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7399daca1d6765cced9baf96ca7c7b85
Autor:
Wieslaw Kuzmicz
Publikováno v:
Electronics; Volume 11; Issue 1; Pages: 6
Electronics, Vol 11, Iss 6, p 6 (2022)
Electronics, Vol 11, Iss 6, p 6 (2022)
Logic gates made of pairs of NPN and PNP bipolar transistors, similar to CMOS logic gates, have been proposed and patented long ago but did not find any practical application until now. Other bipolar technologies (TTL, TTL-S, ECL), once the technolog
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::295ac9760073eb37af731edbf506bb09
Autor:
Wieslaw Kuzmicz
Publikováno v:
Electronics
Volume 10
Issue 15
Electronics, Vol 10, Iss 1800, p 1800 (2021)
Volume 10
Issue 15
Electronics, Vol 10, Iss 1800, p 1800 (2021)
Negative feedback applied to the back gate of MOS devices available in FD-SOI (fully depleted silicon on insulator) CMOS technologies can be used to improve the linearity of operational amplifiers. Two operational amplifiers designed and fabricated i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c8e96721864859be8022ac7a1b791dc8
Autor:
Wieslaw Kuzmicz
Publikováno v:
The International Journal of Electrical Engineering & Education. :002072092199658
This paper describes observations and experiences collected during 14 years of running the “Integrated circuits” course in the framework of a distance learning program. The main objective of the “Integrated circuits” course is to raise the in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f031152e21d09616ed063c38ba519eeb
https://doi.org/10.1177/0020720921996588
https://doi.org/10.1177/0020720921996588
Autor:
Wieslaw Kuzmicz, Zbigniew Jaworski
Publikováno v:
PRZEGLĄD TELEKOMUNIKACYJNY - WIADOMOŚCI TELEKOMUNIKACYJNE. 1:434-438
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2bece2c52eceb5addf19e06887dfdf11
https://doi.org/10.15199/59.2015.4.108
https://doi.org/10.15199/59.2015.4.108
Autor:
Wieslaw Kuzmicz
Publikováno v:
MIXDES
This paper discusses the industrial and research status of CMOS and CMOS-like commercial and emerging technologies. Effects of scaling on transistor cost, max. system complexity and performance are discussed. Performance of state-of-the-art CMOS VLSI
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::535673721b20d1d547ecd340308d472c
https://doi.org/10.23919/mixdes.2017.8004587
https://doi.org/10.23919/mixdes.2017.8004587
Autor:
Michal Wolodzko, Wieslaw Kuzmicz
Publikováno v:
DDECS
In this paper a low power amplifier for bio-signal acquisition is described. The design takes benefit of UTBB-FDSOI 28nm technology and exploits bulk under the buried oxide as a second gate of FET device. This amplifier exhibits low supply current of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::207d8f61a110c379d640d134a7d3903e
https://doi.org/10.1109/ddecs.2017.7934562
https://doi.org/10.1109/ddecs.2017.7934562
Autor:
Wieslaw Kuzmicz
Publikováno v:
EWDTS
A simple extension to the corner stitching data structure for layouts with arbitrary shapes of layout objects, is proposed. The key difference between the classic corner stitching data structure and all its extensions proposed so far, and the extensi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::05ce05fa3e3e781c46570f8c612fee0a
https://doi.org/10.1109/ewdts.2016.7807626
https://doi.org/10.1109/ewdts.2016.7807626
Autor:
Wieslaw Kuzmicz
Publikováno v:
MIXDES
In analog design MOS transistors are treated as “insulated gate” devices, i.e. devices with zero DC input current. In the era of deep submicron technologies this assumption is no longer valid. In transistors with ultra-thin gate oxide gate tunnel
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b9e2111bacba07412b846db497cc1428
https://doi.org/10.1109/mixdes.2016.7529736
https://doi.org/10.1109/mixdes.2016.7529736
Autor:
Raimund Ubar, Maria Fischerova, Witold A. Pleskacz, T. Cibakova, Jaan Raik, Elena Gramatová, Wieslaw Kuzmicz
Publikováno v:
Microelectronics Reliability. 42:1141-1149
This paper deals with the automatic test pattern generation (ATPG) technique at the higher level using a functional fault model and defect-fault relationship in the form of a defect coverage table at the lower level. The paper contributes to test pat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5eed4966633dca48fd048ace1acb5c50
https://doi.org/10.1016/s0026-2714(02)00080-x
https://doi.org/10.1016/s0026-2714(02)00080-x