Zobrazeno 1 - 10
of 21
pro vyhledávání: '"Werner A. Rausch"'
Autor:
Dongbing Shao, Ravikumar Ramachandran, Dureseti Chidambarrao, Eastman Eric, Matthew Angyal, Rasit O. Topaloglu, Werner A. Rausch
Publikováno v:
SPIE Proceedings.
We demonstrate a tool which can function as an interface between VLSI designers and process-technology engineers throughout the Design-Technology Co-optimization (DTCO) process. This tool uses a Monte Carlo algorithm on the output of lithography simu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::748f619c85eae04311883c0cc7483ec2
https://doi.org/10.1117/12.2258002
https://doi.org/10.1117/12.2258002
Autor:
Weihao Weng, Stephan Grunow, Richard A. Wachnik, Xin Miao, Siddarth A. Krishnan, Ruqiang Bao, Xiuling Li, Keith Kwong Hon Wong, Vijay Narayanan, Werner A. Rausch, Unoh Kwon
Publikováno v:
IEEE Electron Device Letters. 36:384-386
Gate resistance, middle of line resistance, and back end of line resistance in modern metal-gate CMOS increase drastically as the dimensions of the gates, interconnects and vias scale down close to or below the bulk electron mean free paths (MFPs) of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2d93f7d6ae9207e07c422cd51aa30924
https://doi.org/10.1109/led.2015.2404805
https://doi.org/10.1109/led.2015.2404805
Autor:
Anthony I. Chou, Amit Kumar, Jin Cai, Ghavam G. Shahidi, P. Oldiges, Tak H. Ning, Werner A. Rausch, W. Haensch
Publikováno v:
2008 IEEE International SOI Conference.
We demonstrate a simple and novel scheme to achieve high drain breakdown voltage (BV) in a high-speed silicon-on-insulator (SOI) logic technology. In an SOI device with two FETs in series, the common floating node provides a negative feedback that li
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e3fa42b1b200dd22ff57ed1b14aedf22
https://doi.org/10.1109/soi.2008.4656275
https://doi.org/10.1109/soi.2008.4656275
Autor:
Werner A. Rausch, D. Siljenberg, P. Oldiges, Paul Ronsheim, D. Onsongo, M. Passaro, M. Grady, M. Connell
Publikováno v:
2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
Elements such as sodium and potassium can contaminate oxides in semiconductor devices, including buried oxides in Silicon-On-Insulator (SOI) devices. Common fabrication processes use chemicals which contain such contaminants - an example being chemic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d20195395fc1c41ed00bd16c0f0656f
https://doi.org/10.1109/asmc.2007.375101
https://doi.org/10.1109/asmc.2007.375101
Autor:
W. Lai, Steven J. Holmes, Werner A. Rausch, Allen H. Gabor, Karl Paul Muller, Colin J. Brodsky, Ernest Y. Wu, Jeffrey J. Welser, Sujatha Sankaran, Ricardo A. Donaton, S. Wu, Ronald A. DellaGuardia, S.K.H. Fung, W. Yan, S.H. Ku, Steven W. Mittl, Anthony I. Chou, A. Vayshenker, J. Snare, Paul D. Agnello, Len Y. Tsou, Mukesh Khare, Michael A. Gribelyuk, Renee T. Mo, Robert J. Purtell, F. Jamin, P.A. McFarland, Akihisa Sekiguchi, D. Nielsen, D. Wehella-Gamage, Ronald D. Goldblatt, E. Barth, Richard A. Ferguson, Tina Wagner, Dominic J. Schepis, Shreesh Narasimha, Woo-Hyeong Lee, Bruce B. Doris, Percy V. Gilbert, Stephen E. Greco, X. Chen, Sadanand V. Deshpande, Yujun Li
Publikováno v:
Digest. International Electron Devices Meeting.
This paper presents a high performance 90 nm generation SOI CMOS logic technology. Leveraging unique SOI technology features, aggressive ground rules and a tungsten local interconnect rendered the smallest 6T SRAM cell reported to date with a cell ar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a76288235c918aa108b3bc11283b3430
https://doi.org/10.1109/iedm.2002.1175865
https://doi.org/10.1109/iedm.2002.1175865
Autor:
E.C. Jones, Heemyong Park, C. Cabral, Ralph W. Young, Werner A. Rausch, Guy M. Cohen, Christopher P. D'Emic, Paul Ronsheim
Publikováno v:
International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
We present a systematic study on redistribution of B, P, and As in silicon-on-insulator (SOI) during RTA as the top silicon layer is scaled down to /spl sim/0.05 um. New observations are reported on dopant diffusion in the thin SOI layers compared wi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e2bb0f74d0b9c2702db6030ecabdf63d
https://doi.org/10.1109/iedm.1999.824164
https://doi.org/10.1109/iedm.1999.824164
Autor:
David T. Hui, Fariborz Assaderaghi, D. Young, Steven H. Voldman, Vaughn P. Gross, Robert Russell Williams, Chekib Akrout, E. Leobangdung, Ghavam G. Shahidi, J. Howard, L. Warriner, Werner A. Rausch, Melanie J. Sherony, N. Rohrer
Publikováno v:
1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).
Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) semiconductor technology is perceived as a major roadblock for the SOI technology to become a viable mainstream contender for high-performance advanced CMOS semiconductor chips (H
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7a3f6597bae3dcd7e11520d623f369a9
https://doi.org/10.1109/soi.1999.819858
https://doi.org/10.1109/soi.1999.819858
Autor:
Fariborz Assaderaghi, D. K. Sadana, Dominic J. Schepis, Atul C. Ajmera, R. Bolam, Werner A. Rausch, Bijan Davari, Ghavam G. Shahidi, Effendi Leobandung, Lawrence F. Wagner, L. Wissel, K. Wu, Harold J. Hovel
Publikováno v:
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).
Partially-Depleted deep sub-micron CMOS on SOI technology is becoming a mainstream technology. This technology offers 20-35% performance gain over a bulk technology implemented with the same lithography. This paper first reviews the partially-deplete
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d67457eeea74f0a9da5723a37d5618cd
https://doi.org/10.1109/cicc.1999.777303
https://doi.org/10.1109/cicc.1999.777303
Autor:
R. Bolam, Ghavam G. Shahidi, Atul C. Ajmera, Bijan Davari, Werner A. Rausch, Lawrence F. Wagner, Fariborz Assaderaghi, D. Sankus, Kun Wu, Dominic J. Schepis, Effendi Leobandung
Publikováno v:
1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
This partially-depleted (PD) silicon on insulator (SOI) technology results in 20-35% performance gain over a comparable bulk technology. A number of SOI-unique effects that complicate device and circuit design are discussed, along with possible remed
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ff77c27b1911bd70da039ea377f85f68
https://doi.org/10.1109/isscc.1999.759337
https://doi.org/10.1109/isscc.1999.759337
Autor:
Atul C. Ajmera, J. Lasky, A. Bryant, M. Coffey, K. Wu, Harold J. Hovel, R. Bolam, F. Assaderaghi, Effendi Leobandung, Jeffrey W. Sleight, Werner A. Rausch, Dominic J. Schepis, Lawrence F. Wagner, Ghavam G. Shahidi, D. K. Sadana, Bijan Davari
Publikováno v:
1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).
A 0.22 /spl mu/m CMOS on SOI technology, using a nonfully depleted device, is developed. This technology uses the same gate lithography and metallization as a comparable bulk technology, but offers a 20-35% higher performance at the chip level. Furth
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d418c9d1af3fde045666b5ddf70ad35b
https://doi.org/10.1109/vlsit.1999.799317
https://doi.org/10.1109/vlsit.1999.799317