Zobrazeno 1 - 10
of 101
pro vyhledávání: '"Wen-Zen Shen"'
Publikováno v:
Analog Integrated Circuits and Signal Processing. 35:65-78
As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are field-solvers, which are intrinsically more accur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d10d376fd8f1a6daefc49a0cdb3f30d2
https://doi.org/10.1023/a:1023425621006
https://doi.org/10.1023/a:1023425621006
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 8:392-400
In this paper, we propose an iterative area/performance tradeoff algorithm for look-up table (LUT)-based field programmable gate array (FPGA) technology mapping. First, it finds an area-optimized, performance-considered initial network by a modified
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::102c6e66017885f04280b0389c137b35
https://doi.org/10.1109/92.863618
https://doi.org/10.1109/92.863618
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 7:380-391
To characterize the power consumption of a macrocell, a general method involves recording the power consumption of all possible input transition events in the look-up tables. However, though this approach is accurate, the size of the table becomes ve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1705c17b3f8c9626a39f9c504f72048c
https://doi.org/10.1109/92.784099
https://doi.org/10.1109/92.784099
Publikováno v:
IEEE Transactions on Consumer Electronics. 44:187-191
An interpolation method based on the criterion to maximize the smoothness is proposed. In contrast to the conventional approach, where the interpolated signal is made smooth by low-pass filtering, in the proposed method, the smoothness is obtained by
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::64cd367a7ccaa4d2d1df4e6ff9e64df4
https://doi.org/10.1109/30.663746
https://doi.org/10.1109/30.663746
Publikováno v:
IEEE Transactions on Consumer Electronics. 44:108-116
By combining the features of block matching algorithm and block recursive algorithm a new motion estimation method is proposed for the complex motion phenomenon. With the full searching procedure used in the block matching algorithm and the adaptive
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f4b3211054818d87026aa5057b8f1676
https://doi.org/10.1109/30.663736
https://doi.org/10.1109/30.663736
Publikováno v:
IEEE Transactions on Consumer Electronics. 43:1124-1131
A three parameter motion model can better describe the motion trajectory of the picture element in a video sequence. Combining the features of the block process and recursive estimation, a block recursive algorithm is proposed to calculate these thre
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6b46166598449ee65540d44d5726af70
https://doi.org/10.1109/30.642380
https://doi.org/10.1109/30.642380
Autor:
Wen Zen Shen, Gwo-Haur Hwang
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 12:488-496
The untestability cube-number product (UCP), a testability measure that can accurately indicate the extra logic needed in testable programmable logic arrays (PLAs), is discussed. Two UCP-based PLA synthesis algorithms are developed. The first one is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::298dfcd25ea94832b9dc7de909d80aeb
https://doi.org/10.1109/43.229732
https://doi.org/10.1109/43.229732
Publikováno v:
Journal of Electronic Testing. 3:67-78
This paper describes a mixed level, (i.e., switch-level and gate-level) transition fault simulator based on parallel patterns: MT-SIM. The switch-level allows the simulator to treat faults at the transistor level, while the gate-level conserves the s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8d640a43def9e89c9f5914539fe3d2dc
https://doi.org/10.1007/bf00159832
https://doi.org/10.1007/bf00159832
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 10:1559-1568
A study is made of single-fault fault collapsing in sequential logic circuits. Two major phenomena, self-hiding (SH) and delayed reconvergence (DR), which arise from the existence of feedback paths and storage elements in sequential circuits, are ana
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dfb4579999a2855c1b02b154eb22ff52
https://doi.org/10.1109/43.103505
https://doi.org/10.1109/43.103505