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pro vyhledávání: '"Wen-Tze Chuang"'
Autor:
Wen-Tze Chuang, 莊文澤
107
Timing constrain will reduce operational frequency of large integrated circuits or system-on-a-chip, and it is often caused by setup timing violation which would be influenced by dynamic voltage drop, can be referred to as maximum timing pus
Timing constrain will reduce operational frequency of large integrated circuits or system-on-a-chip, and it is often caused by setup timing violation which would be influenced by dynamic voltage drop, can be referred to as maximum timing pus
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/j9nhr6
Autor:
Shi-Tang Liu, Jia-Xian Chen, Yu-Tsung Wu, Chao-Ho Hsieh, Chien-Mo Li, Norman Chang, Ying-Shiun Li, Wen-Tze Chuang
Publikováno v:
2022 23rd International Symposium on Quality Electronic Design (ISQED).
Autor:
Jia-Xian Chen, Shi-Tang Liu, Yu-Tsung Wu, Mu-Ting Wu, Chieo-Mo Li, Norman Chang, Ying-Shiun Li, Wen-Tze Chuang
Publikováno v:
2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC).
Autor:
Karthik Srinivasan, Norman Chang, Akhilesh Kumar, Deqi Zhu, Stephen Pan, Wenbo Xia, Jimin Wen, En-Cih Yang, Wen-Tze Chuang, Ying-Shun Li
Publikováno v:
2020 36th Semiconductor Thermal Measurement, Modeling & Management Symposium (SEMI-THERM).
Accurate prediction of on-chip temperature distribution becomes important for the performance and reliability of upcoming 5G, automotive, and AI chip-package-systems. In particular, a large thermal gradient (the temperature variation across a chip) a