Zobrazeno 1 - 10
of 93
pro vyhledávání: '"Wen-Shiang Liao"'
Publikováno v:
Applied Sciences, Vol 12, Iss 20, p 10519 (2022)
In the deep submicron regime, FinFET successfully suppresses the leakage current using a 3D fin-like channel substrate, which gets depleted and blocks possible leakage as the gate is applied with a bias wholly wrapping the channel. Fortunately, a sca
Externí odkaz:
https://doaj.org/article/a3d38593527e434eb1898f9dad8c7710
Publikováno v:
Crystals, Vol 11, Iss 3, p 262 (2021)
Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio have been developed after integrating a 14Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. Under the lower gate vo
Externí odkaz:
https://doaj.org/article/2bd4f281cefd4065a59b67135d146ffa
Autor:
Wen-Shiang Liao, 廖文翔
102
The design of robustly stabilizing controllers is an important issue in the control area, which focuses on synthesizing a controller to keep the closed-loop system stable and possess a robust performance in the presence of real parametric un
The design of robustly stabilizing controllers is an important issue in the control area, which focuses on synthesizing a controller to keep the closed-loop system stable and possess a robust performance in the presence of real parametric un
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/3vpp32
Autor:
Wen Shiang Liao, Wen-How Lan, Mu-Chun Wang, Chi Hao Lo, Jian-Ming Chen, Tien Szu Shen, Ching Chuan Chou
Publikováno v:
Key Engineering Materials. 843:47-51
Using the electrical-field (E-field) stress at the positive and negative directions to generate the degradation and form the recovery effect is a useful metrology to evaluate the integrity of gate dielectric. This consequence deeply influences the dr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0104b51d01304cacbc8e192446cbc8dd
https://doi.org/10.4028/www.scientific.net/kem.843.47
https://doi.org/10.4028/www.scientific.net/kem.843.47
Publikováno v:
IEEE Transactions on Plasma Science. 47:1145-1151
The electrical characteristics of single Si-fin n-type fin field-effect transistors at the threshold voltage ( ${V} _{\mathbf {T}}$ ) implantation energy 6 and 10 keV in the experimental work were practically extracted and analyzed. In general, the e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::db93e61a60b06c8f61e303f4bdee392e
https://doi.org/10.1109/tps.2018.2876367
https://doi.org/10.1109/tps.2018.2876367
Autor:
Deshi Li, Chii-Wen Chen, Wen-Shiang Liao, Haoshuang Gu, Mu-Chun Wang, Xuecheng Zou, Yue-Gie Liaw
Publikováno v:
Semiconductors. 51:1650-1655
The length of Source/Drain (S/D) extension (LSDE) of nano-node p-channel FinFETs (pFinFETs) on SOI wafer influencing the device performance is exposed, especially in drive current and gate/S/D leakage. In observation, the longer LSDEpFinFET provides
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::35c355f44b8729e1533184789481b715
https://doi.org/10.1134/s1063782617120120
https://doi.org/10.1134/s1063782617120120
Autor:
Cheng-Li Lin, Mu-Chun Wang, Haoshuang Gu, Bin Zhou, Deshi Li, Xuecheng Zou, Wen-Shiang Liao, Yue-Gie Liaw
Publikováno v:
Solid-State Electronics. 126:46-50
Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio (Height/Width = 82.9 nm/8.6 nm) have been developed after integrating a 14 A nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::edf7aa154495e678aba562e452530fbf
https://doi.org/10.1016/j.sse.2016.09.017
https://doi.org/10.1016/j.sse.2016.09.017
Publikováno v:
2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA).
Through the electrical measurement plus the heat stress to enhance the existed or latent defects of FinFETs in the nano-node process flow is a useful metrology. This method not only effectively and timely provides the mapping analysis in a whole wafe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e0830c49f24f3c0654975c7a0d6e1512
https://doi.org/10.1109/ipfa47161.2019.8984910
https://doi.org/10.1109/ipfa47161.2019.8984910
Publikováno v:
Crystals, Vol 11, Iss 262, p 262 (2021)
Crystals
Volume 11
Issue 3
Crystals
Volume 11
Issue 3
Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio have been developed after integrating a 14Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. Under the lower gate vo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::05a60b4e018c414282543b53b546ca10
https://doi.org/10.3390/cryst11030262
https://doi.org/10.3390/cryst11030262
Autor:
Chia-Hsien Chang, Chii-Ruey Lin, Tien-Szu Shen, Ting-Wei Chao, Mu-Chun Wang, Wen-Shiang Liao, Ching-Chuan Chou
Publikováno v:
2018 7th International Symposium on Next Generation Electronics (ISNE).
The leakage of FinFETs with the different features and V t implant energy is observed and strongly related to the previous factors. Due to the process controllability, especially in photo-lithography, the multi-channel shape to promote the drive curr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f3122514622492d1d322ba1a056906d
https://doi.org/10.1109/isne.2018.8394624
https://doi.org/10.1109/isne.2018.8394624