Zobrazeno 1 - 10
of 18
pro vyhledávání: '"Wen Wei Seit"'
Autor:
Hong Cai, Md Hazwani Khairy, Rachel Ang, Linfang Xu, Doris Ng, Nanxi Li, Zhonghua Gu, Anmin Kong, Weiguo Chen, Wen Wei Seit, Eva Wai Leong Ching, Norhanani Jaafar, Huanhuan Wang, Landobasa Y.M. Tobing, Leh Woon Lim, Qingxin Zhang, Lennon Yao Ting Lee
Publikováno v:
Silicon Photonics XVIII.
Autor:
Sharon Pei Siang Lim, Ser Choong Chong, Wen Wei Seit, Jacob Jordan Soh, Sasi Kumar Tippabhotla, Vempati Srinivasa Rao
Publikováno v:
2022 IEEE 24th Electronics Packaging Technology Conference (EPTC).
Publikováno v:
2022 IEEE 24th Electronics Packaging Technology Conference (EPTC).
In this work, we demonstrate the addition of grounding plane into the through silicon via (TSV) integrated ion trap to minimize the ion trap heating by effectively shielding the lossy silicon substrate from RF penetration. Windows are made onto this
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::282c41b0a3645547d9b878c05cc7fedc
https://hdl.handle.net/10356/166181
https://hdl.handle.net/10356/166181
Autor:
Sharon Pei Siang Lim, Ser Choong Chong, David Ho Soon Wee, Wen Wei Seit, Jacob Jordan Soh, Tai Chong Chai
Publikováno v:
2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC).
Publikováno v:
2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC).
Publikováno v:
2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC).
Comprehensive Study of Thermal Impact on Warpage Behaviour of FOWLP with Different Die to Mold Ratio
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
One of the challenges in processing Fan Out Wafer Level Package is the warpage of the Molded Wafer. Some of the fabrication processes such as lithography, coating, etching, and plating could not process wafer with high warpage. Therefore, the molded
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
In this work, we report the heterogenous integration of ion trap on silicon assembled on glass interposer, where TSV, micro-bumps and redistribution layer are implemented and allow for ion trap design with significantly high flexibility. CMOS-compati
Autor:
Yu Dian Lim, Chuan Seng Tan, Luca Guidoni, Jing Tao, Peng Zhao, Wen Wei Seit, Jean-Pierre Likforman, T. Henner, Hongyu Li
Publikováno v:
Applied Physics Letters
Applied Physics Letters, American Institute of Physics, 2021, 118 (12), pp.124003. ⟨10.1063/5.0042531⟩
Applied Physics Letters, American Institute of Physics, 2021, 118 (12), pp.124003. ⟨10.1063/5.0042531⟩
In this study, we report the first Cu-filled through silicon via (TSV) integrated ion trap. TSVs are placed directly underneath electrodes as vertical interconnections between ion trap and a glass interposer, facilitating the arbitrary geometry desig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d8ea0ddbea6b9148df4b5bfb72be1fbd
http://arxiv.org/abs/2101.00869
http://arxiv.org/abs/2101.00869