Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Wei-Sung Chang"'
Autor:
Wei-Sung Chang, 張惟淞
104
Phase-look loops (PLLs) are widely employed in radio and wireline communication system. For advanced communication protocol, fractional frequency synthesis plays a key technique in fine frequency resolution requirement. In this thesis, two f
Phase-look loops (PLLs) are widely employed in radio and wireline communication system. For advanced communication protocol, fractional frequency synthesis plays a key technique in fine frequency resolution requirement. In this thesis, two f
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/00391400344762273125
Autor:
Wei-Sung Chang, 張緯淞
98
This thesis proposes a multi-code rate LDPC decoder in the application of IEEE 802.16e. The utilization rate of memory is very high when the LDPC decoder uses a serial architecture. To reduce the complexity of hardware, the percentage of memo
This thesis proposes a multi-code rate LDPC decoder in the application of IEEE 802.16e. The utilization rate of memory is very high when the LDPC decoder uses a serial architecture. To reduce the complexity of hardware, the percentage of memo
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/51049564635178800076
Autor:
Wei-Sung Chang, Tai-Cheng Lee
Publikováno v:
Selected Topics in Power, RF, and Mixed-Signal ICs ISBN: 9781003339434
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6545889ff33a200b7a31c41f410ed8e0
https://doi.org/10.1201/9781003339434-4
https://doi.org/10.1201/9781003339434-4
Publikováno v:
ISCAS
A 5 GHz outer-loop phase noise filter (PNF) circuit is proposed to suppress phase noise. By using an active delay line (DL) and sampling circuits to perform the delay-sampling (DS) technique, one can further reduce the phase noise at the selected off
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ae0d8e604d7267261af1dd7aca24664a
https://doi.org/10.1109/iscas45731.2020.9181056
https://doi.org/10.1109/iscas45731.2020.9181056
Autor:
Wei-Sung Chang, Tai-Cheng Lee
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 63:1845-1853
An ADC-based digital phase-locked loop (DPLL) assisted by a digital-to-time converter (DTC) is proposed for fractional- $N$ frequency synthesis. A successive approximation register (SAR) ADC is adopted to mimic the operation of the time-to-digital co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2226787de8475124246fbefdb25ba2d6
https://doi.org/10.1109/tcsi.2016.2599516
https://doi.org/10.1109/tcsi.2016.2599516
Publikováno v:
IEEE Journal of Solid-State Circuits. 49:2964-2975
A low-noise divider-less PLL, employing a subsampling locked loop, samples the VCO output by a digital pulse-width modulator (DPWM) to perform fractional-N operation. The frequency synthesizer achieves a low in-band phase noise of -112 dBc/Hz at a 2.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2d8037e12f9f04880ee7422363a8b99d
https://doi.org/10.1109/jssc.2014.2359670
https://doi.org/10.1109/jssc.2014.2359670
Publikováno v:
A-SSCC
An energy-efficient self-charged crystal oscillator (SCXO) employing a quadrature-phase shifter is proposed to provide wide-range pulse injection timing for power consumption reduction. The passive resistors of quadrature-phase shifter can be shared
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::604bf6aba8210a9b1e6eba0aba2c7bb5
https://doi.org/10.1109/asscc.2017.8240214
https://doi.org/10.1109/asscc.2017.8240214
Publikováno v:
2017 Symposium on VLSI Circuits.
An LC-VCO-based MDLL is presented in a fractional-N frequency synthesizer to extend its frequency multiplication factor and performance. By employing the proposed MUXs in the LC-VCO, it increases the loop bandwidth (BW) from 3MHz to 15MHz (nearly 0.4
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e152e2ace249852f150437bae4af0d2a
https://doi.org/10.23919/vlsic.2017.8008458
https://doi.org/10.23919/vlsic.2017.8008458
Publikováno v:
2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).
A low-power serializing transmitter is proposed by using a 2.5:1 multiplexer. Owing to its fractional multiplexing operation, only a single clock is needed to simplify the clock generator design as well as hardware cost. Fabricated in a 40 nm CMOS te
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e1bedeb764dc57d8f3a6d5dead38d93a
https://doi.org/10.1109/vlsi-dat.2016.7482532
https://doi.org/10.1109/vlsi-dat.2016.7482532
Publikováno v:
VLSI-DAT
A 3X-oversampling hybrid clock and data recovery (CDR) circuit with programmable bandwidth has been fabricated in a 55-nm CMOS technology. The jitter tolerance analysis and the design of the proposed architecture are presented. The proposed hybrid CD
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e1f709362c69b483695a9bb43badbf54
https://doi.org/10.1109/vlsi-dat.2014.6834881
https://doi.org/10.1109/vlsi-dat.2014.6834881