Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Wei-Sheng Ding"'
Autor:
Wei-Sheng Ding, 丁瑋陞
101
This thesis presents a novel technique that modifies ATPG test patterns to reduce time-averaged IR drop of a test pattern in capture cycles. We propose a FAIR estimation, which is very close to the time-averaged IR drop of time-consuming tra
This thesis presents a novel technique that modifies ATPG test patterns to reduce time-averaged IR drop of a test pattern in capture cycles. We propose a FAIR estimation, which is very close to the time-averaged IR drop of time-consuming tra
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/04766404322555610222
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24:38-49
This paper presents a novel technique that modifies automatic test pattern generation test patterns to reduce time-averaged IR drop of a test pattern. We propose a fast average IR drop estimation, which is very close to the time-averaged IR drop of t
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22:1980-1989
Autor:
Min-Hong Tsai, James Chien-Mo Li, Hung-Chun Li, Ming-Tung Chang, Chih-Mou Tseng, Wei-Sheng Ding, Yu-Chiuan Huang, Min-Hsiu Tsai
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32:644-652
This paper presents a design for testability technique to avoid scan shift failure due to flip-flop simultaneous triggering. The proposed technique changes test clock domains of flip-flops in the regions where severe IR-drop problems occur. A massive