Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Wei-Jin Dai"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 18:1487-1495
In this paper, we introduce a method that uses the field programmable gate array (FPGA)-based emulation system for fault grading. The real-time simulation capability of a hardware emulator could significantly improve the performance of fault grading,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::98fcf88e708dd327291319ccf66228fb
https://doi.org/10.1109/43.790625
https://doi.org/10.1109/43.790625
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 14:1085-1092
Given a system represented at gate level, we propose an algorithm mapping the design into the minimum number of FPGA's for logic emulation. We first devise a Local Ratio-cut clustering scheme to reduce the circuit complexity. Then a Set Covering part
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::41cddb6852c4f16bb14784a983962510
https://doi.org/10.1109/43.406710
https://doi.org/10.1109/43.406710
Publikováno v:
Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7b68cf80fa188089e5a9367357967ef2
https://doi.org/10.1109/aspdac.2003.1195101
https://doi.org/10.1109/aspdac.2003.1195101
Autor:
Wei-Jin Dai, M. Courtoy
Publikováno v:
ISQED
A design methodology for the implementation of multimillion gate system-on-chip designs is described The new methodology is based on the creation of a physical prototype early in the back-end design process. The prototype is generated in a fraction o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7da5319ba820bf09728703658e050e96
https://doi.org/10.1109/isqed.2002.996799
https://doi.org/10.1109/isqed.2002.996799
Publikováno v:
ASP-DAC
A design methodology for the implementation of multi-million gate system-on-chip designs is described. The new methodology is based on the creation of a silicon virtual prototype early in the back-end design process. The prototype is generated in a f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::73ed1b16af13cc7cd2cd38ac5ce5ffb6
https://doi.org/10.1145/1119772.1119916
https://doi.org/10.1145/1119772.1119916
Autor:
Wei-Jin Dai
Publikováno v:
ISPD
In this paper, a design methodology for the implementation of multi-million gate system-on-chip designs is described.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eefe6a9ef560d5c372e8a8232d79b51e
https://doi.org/10.1145/369691.369766
https://doi.org/10.1145/369691.369766
Publikováno v:
DAC
Given a huge system represented at gate level, we propose an algorithm mapping the design into the minimum number of FPGAs for logic emulation. We first devise a Local Ratio-cut clustering scheme to reduce the circuit complexity. Then a Set Covering
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0264f69df62d7a5e5976c346d124f1e1
https://doi.org/10.1145/196244.196365
https://doi.org/10.1145/196244.196365
Publikováno v:
Proceedings of the ASP-DAC Asia & South Pacific Design Automation Conference, 2003; 2003, p635-639, 5p
Autor:
Wei-Jin Dai, Courtoy, M.
Publikováno v:
Proceedings International Symposium on Quality Electronic Design; 2002, p529-533, 5p
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; 1995, Vol. 14 Issue 9, p1085-1092, 8p