Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Wei-Jen Hsia"'
Publikováno v:
Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130); 2000, p403-406, 4p
Autor:
E. Li, W.C. Yeh, Venkatesh P. Gopinath, A. Badowski, Sharad Prasad, Mohammad R. Mirabedini, Arvind Kamath, B. Baylis, Wilbur G. Catabay, Wei-jen Hsia, Y. Le, O. Kobozeva, Ming-Yi Lee, J. Haywood, Verne Hornback
Publikováno v:
2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..
This paper describes a 90 nm System-on-a-chip (SoC) technology with modular quadruple gate oxides (16, 28, 50, 64 /spl Aring/) on the same chip allowing integration of optimized transistors operating at supply voltages of 1, 1.2, 1.8, 2.5 and 3.3 Vol
Autor:
P. Li, Jayanthi Pallinti, J. Koh, T. Fujimoto, Chuan-cheng Cheng, W. Catabay, M. Lu, Mei Zhu, Hao Cui, S. Neumann, Wei-jen Hsia, P. Wright
Publikováno v:
Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).
The first process integration of Cu metallization and next generation CVD ultra low k (Trikon Orion ULK, k=2.2) is presented. The current process condition for a 130 nm node Cu/lowk (k=2.9) process is applied to Cu/ULK and found to be suitable withou
Publikováno v:
Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130).
In the development of interconnect architecture for future technologies, LSI has determined that adoption of low-k dielectrics will give higher performance gain as opposed to the replacement of aluminum with copper. The goal is to integrate a robust
Autor:
Chuan-cheng Cheng, Wei-jen Hsia, Pallinti, J., Neumann, S., Koh, J., Li, P., Mei Zhu, Lu, M., Hao Cui, Fujimoto, T., Catabay, W., Wright, P.
Publikováno v:
Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519); 2002, p256-258, 3p
Autor:
Toshitake Tsuda, David Pachura, Sharad Prasad, Mohammad R. Mirabedini, Verne Hornback, Wilbur G. Catabay, Masanobu Matsunaga, Erhong Li, Hong Lin, Jim Elmer, Wai Lo, Lesly Duong, Wei-jen Hsia, Joyce Lin, Colin Yates, Venkatesh P. Gopinath
Publikováno v:
Journal of The Electrochemical Society. 152:G110
Polycrystalline Si 1 - x Ge x (poly-SiGe) is a known gate electrode material that can mitigate poly-depletion effects, which exist in deep submicrometer complementary metal-oxide-semiconductor (CMOS) transistors, due to its lower dopant activation te
Publikováno v:
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures. 20:1987
Drift of copper (Cu) ions into methyl-doped silicon oxide film, a promising low-dielectric-constant (low-κ) material for inter-layer dielectrics applications in ultralarge scale integrated circuit (ULSI) interconnects, was investigated using bias te
Autor:
Weidan Li, Hongqiang Lu, Hao Cui, Wei-jen Hsia, Shyam P. Murarka, Ishwara B. Bhat, Williams Lanford
Publikováno v:
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures. 20:828
In this article, methyl-doped silicon oxide films deposited using Flowfill™ chemical vapor deposition (CVD) technology have been chracterized for use in inter-layer dielectrics application. Films with different methyl concentrations were deposited
Autor:
Wilbur G. Catabay, Hao Cui, Ishwara B. Bhat, Weidan Li, Wei-jen Hsia, Shyam P. Murarka, Hongqiang Lu
Publikováno v:
Journal of The Electrochemical Society. 147:3816
In this work, the properties and chemical mechanical polishing (CMP) characteristics of thin films of a new low dielectric constant (low-κ) oxide deposited using Flowfill chemical vapor deposition (CVD) technology are presented. This oxide film cons
Autor:
Nobuyoshi Sato, Yukihiro Shimogaki
Publikováno v:
ECS Journal of Solid State Science & Technology; 2014, Vol. 3 Issue 1, pN3041-N3045, 5p