Zobrazeno 1 - 10
of 67
pro vyhledávání: '"Warren W. Flack"'
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
Wafer-level packaging with high density fan-out (HDFO) requires multiple redistribution layers (RDL) to handle the high-density interconnections and the large data transfer rates between chips in the package. Decreasing the critical dimension (CD) of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d28c73578bba241778250a7175cea319
https://doi.org/10.1109/ectc32862.2020.00179
https://doi.org/10.1109/ectc32862.2020.00179
Autor:
Andy Miller, Akito Hiro, Romain Ridremont, John Slabbekoorn, Samuel Suhard, Robert Hsieh, Warren W. Flack, Ha-Ai Nguyen
Publikováno v:
2018 IEEE 20th Electronics Packaging Technology Conference (EPTC).
This study investigates creation of $1.0 \mu \mathrm{m}$ RDL structures by a damascene process utilizing a photosensitive permanent dielectric material. The advantage of the photosensitive dielectric approach is that the Cu overburden removal does no
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6169bd12f6aa5c0f286fbd515d9223c4
https://doi.org/10.1109/eptc.2018.8654363
https://doi.org/10.1109/eptc.2018.8654363
Publikováno v:
2017 IEEE 19th Electronics Packaging Technology Conference (EPTC).
Fan-Out wafer level packaging has seen rapid adoption over the last few years due to its form factor, performance, and cost advantages compared to 3D packaging techniques. Redistribution layers (RDL) are used to route the very high density connection
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8202099928c9d84ea4f5adaf2e7d8811
https://doi.org/10.1109/eptc.2017.8277536
https://doi.org/10.1109/eptc.2017.8277536
Autor:
John Slabbekoorn, Bert Tobback, Andy Miller, Warren W. Flack, P. Czarnecki, Gareth Kenyon, Michele Stucchi, Stefaan Van Huylenbroeck, T. Vandeweyer, Robert Hsieh
Publikováno v:
2016 IEEE 18th Electronics Packaging Technology Conference (EPTC).
Foundry customers and makers of leading-edge devices are evaluating through-silicon via (TSV) for next-generation three-dimensional (3D) packaging. Scaling the diameter of the TSV is a major driver for improving system performance and cost. With smal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::14edb796fc57e2f9bd0d4e0c0bf428b2
https://doi.org/10.1109/eptc.2016.7861543
https://doi.org/10.1109/eptc.2016.7861543
Autor:
John Slabbekoorn, Yi Cao, Chunwei Chen, Robert Hsieh, Warren W. Flack, Andy Miller, Gareth Kenyon, Ping-Hung Lu, Eric Beyne, Manish Ranjan, Medhat A. Toukhy
Publikováno v:
2014 IEEE 64th Electronic Components and Technology Conference (ECTC).
Large area silicon or glass interposers may exceed the maximum imaging field of step and repeat lithography tools. This paper discusses the lithographic process used to create a large area interposer on a stepper by the combination of multiple subfie
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e25a0b2fce11fdda5727cf1ae086de01
https://doi.org/10.1109/ectc.2014.6897262
https://doi.org/10.1109/ectc.2014.6897262
Autor:
Khiem T. Nguyen, Nuno Silva, Paulo Cardoso, Eoin O Toole, Robert Hsieh, Gareth Kenyon, Manish Ranjan, Werner Robl, Warren W. Flack, Rainer Leuschner, Thorsten Meyer
Publikováno v:
2011 IEEE 61st Electronic Components and Technology Conference (ECTC).
The rapid growth of wireless consumer electronics products is driving demand for cost effective and small form factor packaging solutions. While front end silicon technologies have followed Moore's law by device scaling, the back end infrastructure h
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::72de898d10e380999ad695485931c573
https://doi.org/10.1109/ectc.2011.5898493
https://doi.org/10.1109/ectc.2011.5898493
Publikováno v:
Proceedings of SPIE.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4c36d8d510649a9e48226aee0098c184
https://doi.org/10.1117/12.711606
https://doi.org/10.1117/12.711606
Publikováno v:
2007 12th International Symposium on Advanced Packaging Materials: Processes, Properties, and Interfaces.
As pin counts and interconnection densities increase there is growing interest in copper pillar bumps for flip chip and wafer-level packaging. This trend is driven by the need to increase interconnect performance as well as reduce interconnect cost.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e335aa9c1d2e69323522cf3c347dde52
https://doi.org/10.1109/isapm.2007.4419942
https://doi.org/10.1109/isapm.2007.4419942
Publikováno v:
SPIE Proceedings.
The requirements for highly specialized photosensitive materials for nanotechnology and Micro-Electro-Mechanical Systems (MEMS) applications are being driven by the rapid growth of consumer products incorporating these devices. These high volume cons
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0183e38f89edf7a7f2a7380e031b6eb5
https://doi.org/10.1117/12.655721
https://doi.org/10.1117/12.655721