Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Wang Shiang-Bau"'
Autor:
Hun-Jan Tao, H. C. Lin, Huan-Just Lin, Lee Chia-Fu, P.C. Yen, C.H. Huang, Yuan-Hung Chiu, W.S. Huang, C. C. Wu, King-Yuen Wong, Chun Chen, Stock Chang, Wang Shiang-Bau, Li-Shiun Chen, S.W. Chuang, Po-Kang Wang, Ming-Jie Huang, X.F. Yu, S.Y. Ku, Chien-Chao Huang, M.L. Cheng, Yung-Huei Lee, K. F. Yu, T.H. Li, C.M. Wu, Y. C. Peng, C.H. Tsai, Y.C. Lin, Tsz-Mei Kwok, Yi-Chun Huang, P.S. Lim, T.C. Gan, Tzong-Lin Wu, K.Y. Hsu, L.Y. Yang, S.S. Lin, L.W. Weng, T.H. Hsieh, F.K. Yang, C.T. Chan, Eric Ou-Yang, P.C. Hsieh, Derek Lin, S.B. Wang, Ming-Jer Chen, A. Keshavarzi, Chih-Yuan Lu, Chuan-Ping Hou, L.T. Lin, J.L. Yang, Yuh-Jier Mii, Chien-Chang Su, J.H. Chen, Hsieh Ching-Hua, Huan-Neng Chen, Y.W. Tseng, C. P. Lin, Chou Chun-Hao, A.S. Chang, Tseng Chien-Hsien, S.H. Liao, Tsung-Lin Lee, M. Cao
Publikováno v:
2010 International Electron Devices Meeting.
A high performance 22/20nm CMOS bulk FinFET achieves the best in-class N/P I on values of 1200/1100 µA/µm for I off =100nA/µm at 1V. Excellent device electrostatic control is demonstrated for gate length (L gate ) down to 20nm. Dual-Epitaxy and mu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b4c6b433e020bd0d422f4c784d225937
https://doi.org/10.1109/iedm.2010.5703430
https://doi.org/10.1109/iedm.2010.5703430
Autor:
Ming-Huan Tsai, Yu-Lien Huang, Li-Te Lin, Wang Shiang-Bau, Hung-Ming Chen, Eric Ou-Yang, Yuh-Jier Mii, Hsien-Hsin Lin, Hun-Jan Tao, Chia-Cheng Ho, Chen-Ping Chen, Jhon-Jhy Liaw, Jyh-Cherng Sheu, Feng Yuan, Chu-Yun Fu, Yi-Hsuan Liu, Li-Shiun Chen, Chia-Feng Hu, Chen-Nan Yeh, Shih-Peng Tai, Ming-Jie Huang, Chih-Sheng Chang, C.H. Chang, Shu-Tine Yang, Jeff J. Xu, Tsung-Lin Lee, Li-Shyue Lai, Shao-Ming Yu, Clement Hsingjen Wann, Kai-Ting Tseng, Leo Chen, Chih-Chieh Yeh, Ming-Feng Shieh, Chien-Chang Su, Jeng-Jung Shen, Shyue-Shyh Lin, Shih-Ting Hung, Hsien-Chin Lin, Shin-Chih Chen, Kin-Weng Wang, Yuan-Hung Chiu, Tsz-Mei Kwok, Fu-Kai Yang
Publikováno v:
2009 IEEE International Electron Devices Meeting (IEDM).
FinFET is the most promising double-gate transistor architecture [1] to extend scaling over planar device. We present a high-performance and low-power FinFET module at 25 nm gate length. When normalized to the actual fin perimeter, N-FinFET and P-Fin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::144d7411e1ccabb3bfe552132a866a0f
https://doi.org/10.1109/iedm.2009.5424367
https://doi.org/10.1109/iedm.2009.5424367
Autor:
Wang, Shiang-Bau.
Thesis (Ph. D.)--University of Wisconsin--Madison, 1999.
Includes bibliographical references (p. 175-183). Also available on the Internet.
Includes bibliographical references (p. 175-183). Also available on the Internet.
Autor:
Wang, Shiang-Bau, Wendt, Amy E.
Publikováno v:
IEEE Transactions on Plasma Science. Oct99, Vol. 27 Issue 5, p1358. 8p. 2 Black and White Photographs, 3 Charts, 4 Graphs.