Zobrazeno 1 - 1
of 1
pro vyhledávání: '"Walter F. J. Muller"'
Publikováno v:
2016 IEEE-NPSS Real Time Conference (RT).
In beam test setups detector elements together with a readout composed of frontend electronics (FEE) and usually a layer of field-programmable gate arrays (FPGAs) are being analyzed. The FEE is in this scenario often directly connected to both the de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::176d532ed372053406209a0bbf87d0e1
https://doi.org/10.1109/rtc.2016.7543119
https://doi.org/10.1109/rtc.2016.7543119
