Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Walker J. Turner"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 57:2898-2908
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6cd9e46029f79d5dd13842100d70b164
https://doi.org/10.1109/jssc.2022.3183208
https://doi.org/10.1109/jssc.2022.3183208
Autor:
Hao Chen, Kai-Chieh Hsu, Walker J. Turner, Po-Hsuan Wei, Keren Zhu, David Z. Pan, Haoxing Ren
Publikováno v:
Proceedings of the 2023 International Symposium on Physical Design.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0c6bcc6823c804f61652ed160e8eff99
https://doi.org/10.1145/3569052.3571874
https://doi.org/10.1145/3569052.3571874
Autor:
Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray
Publikováno v:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4b073895224567cb6ac5cc709f4ada51
https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830174
https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830174
Autor:
Hao Chen, Walker J. Turner, Sanquan Song, Keren Zhu, George F. Kokai, Brian Zimmer, C. Thomas Gray, Brucek Khailany, David Z. Pan, Haoxing Ren
Publikováno v:
Proceedings of the 2022 International Symposium on Physical Design.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d3a4c60316e8c638f4c6100bb003e4b8
https://doi.org/10.1145/3505170.3511044
https://doi.org/10.1145/3505170.3511044
Autor:
William J. Dally, C. Thomas Gray, John Wilson, Sudhir S. Kudva, John W. Poulton, Wenxu Zhao, Nikola Nedovic, Stephen G. Tell, Xi Chen, Walker J. Turner, Sunil Sudhakaran, Sanquan Song, Brian Zimmer
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:43-54
This paper describes a short-reach serial link to connect chips mounted on the same package or on neighboring packages on a printed circuit board (PCB). The link employs an energy-efficient, single-ended ground-referenced signaling scheme. Implemente
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::70a389957702df6b0d96ce08d434e6fc
https://doi.org/10.1109/jssc.2018.2875092
https://doi.org/10.1109/jssc.2018.2875092
Publikováno v:
IEEE Solid-State Circuits Magazine. 11:54-68
As the end of the Moore's law era approaches, increases in computational perfor mance can no longer rely on the historical scaling of integrated circuit feature sizes that the industry has depended on for the last half century. This reduction in scal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ea8accc68e7f4ad7984ba650202f6460
https://doi.org/10.1109/mssc.2019.2910618
https://doi.org/10.1109/mssc.2019.2910618
Publikováno v:
DATE
Layout parasitics significantly impact the performance of analog integrated circuits, leading to discrepancies between schematic and post-layout performance and requiring several iterations to achieve design convergence. Prior work has accounted for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d42af9562d9504bafd7af3625c1ff1f1
https://doi.org/10.23919/date51398.2021.9474253
https://doi.org/10.23919/date51398.2021.9474253
Publikováno v:
DAC
Layout-dependent parasitics and device parameters significantly impact integrated circuit performance and are often the cause of slow convergences between schematic and layout designs. Circuit designers typically estimate parasitics from past experie
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::460b88348c693483266e5ac6f0918e90
https://doi.org/10.1109/dac18072.2020.9218515
https://doi.org/10.1109/dac18072.2020.9218515
Autor:
C. Thomas Gray, Brian Zimmer, Thomas Hastings Greer, John Wilson, Stephen G. Tell, Xi Chen, Sudhir S. Kudva, John W. Poulton, Sanquan Song, Nikola Nedovic, Walker J. Turner
Publikováno v:
ISSCC
A recent trend in high-performance systems is distribution of computing across many chips and packages to sustain performance scaling while achieving high yield and alleviating power delivery. High-end data center systems and new applications like de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::449583e02cadafa70b50c7f34587775e
https://doi.org/10.1109/isscc19947.2020.9063140
https://doi.org/10.1109/isscc19947.2020.9063140
Autor:
Sudhir S. Kudva, William J. Dally, Brian Zimmer, Stephen G. Tell, Xi Chen, John W. Poulton, Walker J. Turner, Nikola Nedovic, C. Thomas Gray, Sanquan Song, John Wilson
Publikováno v:
CICC
To support high-speed IOs, a 2-to-20 GHz cross-coupled inverter-based multi-phase PLL with phase interpolators using injection-locked oscillation buffers is presented. The proposed voltage-controlled oscillator (VCO) is made of two 4-stage ring oscil
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::de8579a51a1333ffd73deb84bc098be6
https://doi.org/10.1109/cicc.2019.8780177
https://doi.org/10.1109/cicc.2019.8780177