Zobrazeno 1 - 10
of 86
pro vyhledávání: '"Waisum Wong"'
Autor:
Baokang Peng, Yanxin Jiao, Haotian Zhong, Zhao Rong, Zirui Wang, Ying Xiao, Waisum Wong, Lining Zhang, Runsheng Wang, Ru Huang
Publikováno v:
Fundamental Research; Sep2024, Vol. 4 Issue 5, p1306-1313, 8p
Autor:
Baokang Peng, Yanxin Jiao, Haotian Zhong, Zhao Rong, Zirui Wang, Ying Xiao, Waisum Wong, Lining Zhang, Runsheng Wang, Ru Huang
Publikováno v:
Fundamental Research.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c9c48cf9d387a45d4b33cd2999030613
https://doi.org/10.1016/j.fmre.2022.09.035
https://doi.org/10.1016/j.fmre.2022.09.035
Autor:
Xiaojin Li, Yabin Sun, Zhen Zhou, Lijie Sun, Guangxing Wan, Waisum Wong, Mengying Zhang, Yanling Shi
Publikováno v:
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT).
In this work, we propose a novel RC tightened corner test structure for FinFET Technology. In this test structure, Parasitic RC DUTs (Design Under Test) integrated into RO (Ring Oscillator) have been designed to verify and calibrate MEOL (Mid-End-Of-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2110e18a8197e1d63df62a86c3918362
https://doi.org/10.1109/icsict49897.2020.9278392
https://doi.org/10.1109/icsict49897.2020.9278392
Publikováno v:
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
In this paper, a novel method is demonstrated to provide quantitative analysis of layout dependent effects (LDE) on Standard cell (Stdcell) devices. The impact of each LDE was split by model simulation and correlated with silicon statistics of over 3
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d50a6a51d727ede70f753533a7b431fd
https://doi.org/10.1109/icsict.2018.8565667
https://doi.org/10.1109/icsict.2018.8565667
Publikováno v:
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
In this work, a novel RC tightened corner modeling methodology using statistical simulation is proposed for the advanced FinFET technology. Based on foundries’ parasitic RC techfile, MEOL (Middle-End-Of- Line) and BEOL (Back-End-Of-Line) parasitic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::00b722e9fb917b71d880113c6a227821
https://doi.org/10.1109/icsict.2018.8564960
https://doi.org/10.1109/icsict.2018.8564960
Autor:
Yu Xia, Xiao-wei Zou, Stephane Badel, Wen Yang, Xiang-Qiang Zhang, Zanfeng Chen, Liu Yanxiang, Meng Lin, Ma Xiaolong, Wei Wei, Miao Xu, Zeng Qiuling, Waisum Wong, Yong Yu, Paak Sunhom Steve, Wei Zheng
Publikováno v:
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
The diffusion break (DB) induced layout effect is one of the major culprits for device variability and deteriorators for chip Vmin and Iddq. For the first time, the performance and leakage impacts from varied types of diffusion breaks are quantified
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::686bd0299a7dd4e08954eed4a2ee818f
https://doi.org/10.1109/icsict.2018.8565694
https://doi.org/10.1109/icsict.2018.8565694
Publikováno v:
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
SOC (System on Chip) timing closure meets challenges in advanced FinFet technologies with lower voltage and higher frequency. As a part of variation, aging is taking more attention. But capturing the effect of BTI (includes NBTI and PBTI) on timing h
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::943aa9e9e9ad52308c9029f508f119ae
https://doi.org/10.1109/icsict.2018.8565644
https://doi.org/10.1109/icsict.2018.8565644
Autor:
Yu Qianmin, Zhao Zicai, Zou Xiaowei, Waisum Wong, Cheng Changhong, Li Zan, Sun Lijie, Yu Yong
Publikováno v:
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
Double Patterning (DP) is imperative process for FinFET, and Metal-Oxide-Metal (MoM) capacitors are crucial passive devices in mixed-signal/analog integrated circuits, the process variation of DP is increased by Metal space, width and dielectrics con
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7e7cf15c02f4aed082791262221596da
https://doi.org/10.1109/icsict.2018.8564813
https://doi.org/10.1109/icsict.2018.8564813
Autor:
Changze Liu, Zhenghao Gan, Dan Gao, Canhui Zhan, Yu Xia, Waisum Wong, Pengpeng Ren, Zanfeng Chen
Publikováno v:
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
Off-state device degradation has attracted growing attention in advanced technology node. In this paper, off-state stress induced degradation is comprehensively studied in ultra-scaled FinFETs. Based on the proposed characterization method, new degra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::abe3a4af4549bd2bd9045ac95b85714e
https://doi.org/10.1109/icsict.2018.8564811
https://doi.org/10.1109/icsict.2018.8564811
Publikováno v:
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC).
In this work, a Parasitic Extraction (PEX) verification methodology and flow for a middle-end-of-line (MEOL) gate-around parasitic capacitance has been developed for Advanced FinFET technologies. Our work focus on the verifying the extraction accurac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ac3421d0cce0cce0a196baf23974f161
https://doi.org/10.1109/edssc.2018.8487070
https://doi.org/10.1109/edssc.2018.8487070