Zobrazeno 1 - 10 of 33 pro vyhledávání: '"W.Y. Lien"'
1
Analysis and experiment of non-Darcian convection in horizontal square packed-sphere channels—II. Mixed convection
Autor: C.J. Cheng, W.Y. Lien, F.C. Chou
Publikováno v: International Journal of Heat and Mass Transfer. 35:1197-1207
This paper presents an analysis and experiment of fully developed non-Darcian mixed convection in horizontal packed-sphere channels. The non-Darcian effects of no-slip boundary, flow inertia, channeling and thermal dispersion are considered. The theo
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::15dfe28443f8761e5514956aaba9a943
https://doi.org/10.1016/0017-9310(92)90179-v
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2
Analysis and experiment of non-Darcian convection in horizontal square packed-sphere channels—1. Forced convection
Autor: S.H. Lin, F.C. Chou, W.Y. Lien
Publikováno v: International Journal of Heat and Mass Transfer. 35:195-205
A numerical and experimental investigation of non-Darcian forced convection in horizontal square packed-sphere channels is presented. The theoretical results are found to be in agreement with the experimental results. The values of the fully-develope
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::542e05bfad6d3cb0d1e454cd874749b1
https://doi.org/10.1016/0017-9310(92)90020-s
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3
45nm SOI CMOS Technology with 3X hole mobility enhancement and Asymmetric transistor for high performance CPU application
Autor: F.L. Hsiao, W.Y. Lien, C.T. Li, Y.C. Sun, T.L. Chen, K.C. Wu, Y.H. Chiu, H.J. Tao, C.H. Huang, K.H. Chen, P.W. Wang, C.H. Wu, L.T. Lin, Yuh-Jier Mii, H.C. Tuan, Y.H. Liu, I.L. Wu, H.C. Lo, D.H. Lee, W.Y. Lu, C.F. Cheng, K.Y. Chen, S.K.H. Fung
Publikováno v: 2007 IEEE International Electron Devices Meeting.
45 nm SOI CMOS technology target for high performance CPU application is reported. Process induced strained CMOS demonstrates 1232/855 uA/um DC Ion at 100 nA/um Ioff under Vdd=lV, which is the highest ever reported performance at 45 nm ground rule fo
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0639b1de7274beda31aba4692a9f2930
https://doi.org/10.1109/iedm.2007.4418928
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4
A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm2 SRAM cell
Autor: W. Chang, P.W. Wang, Ming-Ta Lei, K. Goto, H.C. Hsieh, C.H. Diaz, W.Y. Lien, S.C. Wang, H.Y. Huang, Hun-Jan Tao, Y.H. Chang, C.H. Yeh, L.T. Lin, D.Y. Lee, C.C. Wu, S.P. Fu, Y.H. Chiu, J.H. Chen, M.H. Hsieh, Y.P. Wang, C.T. Lin, Che-Min Chu, H.H. Lin, S.Y. Lu, Y.J. Mii, S.J. Yang, Chun-Kuang Chen, C.F. Nieh, Y.Y. Tarng, Kuan-Lun Cheng, M. Cao, Chii-Ming Wu, H.C. Tuan, D.W. Lin, M.J. Huang, F.C. Chen, C.M. Liu, M.Y. Wang
Publikováno v: 2007 IEEE International Electron Devices Meeting.
A highly scaled, high performance 45 nm CMOS technology utilizing extensive immersion lithography to achieve the industry's highest scaling factor with ELK (k=2.55) BEOL is presented. A record gate density 2.4X higher than that of 65 nm is achieved.
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::166dfe572d93dc05f186c9f2320a2e52
https://doi.org/10.1109/iedm.2007.4418913
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5
A Ku-band CMOS low-noise amplifier
Autor: S.H. Wang, W.Y. Lien, Chin-Shen Lin, Kuo-Liang Deng, Huei Wang, G.J. Chem, Ming-Da Tsai, Kun-You Lin
Publikováno v: 2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks.
A Ku-band monolithic low-noise amplifier is presented in this paper. This LNA fabricated in commercial 0.18-/spl mu/m CMOS technology is a two-stage common-source design instead of cascode configuration for lower noise performance. This CMOS LNA demo
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7bfa5f6083c429021b90f8175011d08c
https://doi.org/10.1109/rfit.2005.1598906
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6
A 90 nm CMOS MS/RF based foundry SOC technology comprising superb 185 GHz f/sub T/ RFMOS and versatile, high-Q passive components for cost/performance optimization
Autor: G.J. Chern, H.C. Lin, T.Y. Lin, D.D. Tang, C.L. Chang, C.T. Lin, H.J. Lin, S.H. Wang, J.C. Guo, M.C. King, C.H. Chen, M.Y. Wei, C.F. Chen, C.F. Huang, W.Y. Lien, C.S. Chang, J.C.H. Lin, Y.C. Tsai, M.R. Tsai, C.M. Huang, Y.J. Wang, P.M. Tseng, H.M. Hsu, C.C. Wu, W.M. Chen, C.F. Chang, C.C. Ku, S.M. Chen, C.W. Chen, S. Chen, C.C. Chang, J.Y.C. Sun, J.F. Kuan, C.P. Chao
Publikováno v: IEEE International Electron Devices Meeting 2003.
A versatile mixed-signal and RF (MS/RF) technology based on a foundry 90 nm CMOS process was demonstrated with excellent MOS transistor f/sub T/ at 160-185 GHz. Passive elements of various process schemes were fabricated for cost/performance evaluati
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::da66597ec7cbb937b936f0f912e3bdd3
https://doi.org/10.1109/iedm.2003.1269161
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7
The integration of proton bombardment process into the manufacturing of mixed-signal/RF chips
Autor: H.M. Hsu, C.M. Wu, W.C. Lin, C.W. Chang, Y.C. Sun, G.J. Chern, L.F. Lin, C.S. Chang, K.C. Lan, D.D. Tang, C.P. Chao, J.C. Guo, L.P. Lee, C.Y. Lee, W.Y. Lien, D.S. Du, L.S. Lai, C.H. Wang
Publikováno v: IEEE International Electron Devices Meeting 2003.
Proton bombardment technology is integrated into the standard IC process as a post-backend process module to form local semi-insulating regions on mixed-signal/RF chips. With 10/sup 15/ cm/sup -2/, 100 /spl mu/m deep bombardment through mask windows,
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f6014a7a4884ab50e8dd32f92e612d9a
https://doi.org/10.1109/iedm.2003.1269370
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8
Low-K/Cu CMOS logic based SoC technology for 10 Gb transceiver with 115 GHz f/sub T/, 80 GHz f/sub MAX/ RF CMOS, high-Q MiM capacitor and spiral Cu inductor
Autor: M.C. Hung, W.Y. Lien, C.W. Chen, Ping Yang, Y.C. Sun, C.M. Wu, C.C. Liu, J.C. Guo
Publikováno v: 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).
For the first time, foundry CMOS logic based RF technology is introduced for 10 Gb/s transceiver in which active and passive RF elements have been realized in a single chip. Superior RF CMOS of 115 GHz f/sub r/, 80 GHz f/sub MAX/, and 2.2 dB NF/sub m
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1cb925e45dddadc94c86aa9ae3bd0e94
https://doi.org/10.1109/vlsit.2003.1221075
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10
A robust shallow trench isolation (STI) with SiN pull-back process for advanced DRAM technology
Autor: H.F. Lee, K.C. Tu, W.J. Liang, I.H. Chang, H.M. Chou, H.C. Chu, M.H. Tsai, M.H. Chi, W.G. Yeh, C.Y. Chen, W.R. Liaw, C.H. Li, W.Y. Lien
Publikováno v: 13th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference. Advancing the Science and Technology of Semiconductor Manufacturing. ASMC 2002 (Cat. No.02CH37259).
In this paper, the effect of SiN pull-back process for shallow trench isolation (STI) is investigated by measuring DRAM array's refresh time (Tref) and yield as sensitive monitors. The SiN pull-back is performed by using H/sub 3/PO/sub 4/ solution af
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d3a383044a9dec0e5cf9f46dcec31f4f
https://doi.org/10.1109/asmc.2002.1001567
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