Výsledky vyhledávání

Substrate current characterization and optimization of high voltage LDMOS transistors

Autor: Xin Zou, Rui Li, Yemin Dong, Jun Wang, Li Shao, W.T. Shiau

Publikováno v: Solid-State Electronics. 52:886-891

A 30-V LDMOS integrated with a standard 0.15 μm CMOS process is investigated for its double-hump substrate current ( I b ) characteristics. The origin of this abnormal second substrate current hump is explained by Kirk effect. The impact of this sec

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d4d114bc188f7d5b40b67922e31900e1
https://doi.org/10.1016/j.sse.2008.01.018

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A new insight into the degradation mechanisms of various mobility-enhanced cmos devices with different substrate engineering

Autor: Yu-Wei Liu, Steve S. Chung, C.T. Tsai, S.C. Chien, S.J. Wu, W.T. Shiau, Y.C. Liu, H.S. Lin, D.F. Chen, Chao-Sung Lai, S.W. Sun

Publikováno v: Scopus-Elsevier

In this paper, the difference in degradation mechanism for different substrate engineered CMOS devices has been reported for the first time. These two different substrate engineering includes hybrid substrate engineering, with (100) and (110) orienta

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ee5c95e73f216d891b1851d4d7ede3c5
https://doi.org/10.1109/iedm.2005.1609407

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Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range

Autor: C. L. Yang, Steve S. Chung, Kuan Liao, Hsien-Tsung Feng, D.F. Chen, A. Liu, S.C. Chien, D.Y. Wu, W.T. Shiau, S.W. Sun, Y.S. Hsich, Y.C. Sheng, Osbert Cheng, K.T. Huang, J.H. Ho, W.M. Lin

Publikováno v: IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

A low leakage characterization technique for the lateral profiling of interface and oxide traps in a 12A-16A range gate oxide CMOS device has been demonstrated. The approach being taken includes an incremental frequency charge-pumping (IFCP) measurem

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::ea5c2ce45f22a4dee487363d1f5027e0
https://doi.org/10.1109/iedm.2004.1419193

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Investigation and Modeling of Stress Interactions on 90 nm SOI CMOS with Various Mobility Enhancement Approaches

Autor: Wen-Kuan Yeh, Liang-Wei Chen, Huan-Cheng Chang, C. T. Tsai, Chien-Ting Lin, Che-Hua Hsu, M. L. Lee, W.T. Shiau, Yean-Kuen Fang

Publikováno v: Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3943d102d3acfa20401e9465d26696ec
https://doi.org/10.7567/ssdm.2005.p3-14

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Performance of 70 nm strained-silicon CMOS devices

Publikováno v: 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

An 86% electron mobility improvement and over 20% I/sub dn-sat/ enhancement were demonstrated for a 70 nm strained-Si CMOS process fabricated on SiGe virtual substrates. Compared to a bulk-Si CMOS process, the strained-Si process delivered 95% higher

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2509726fa79ce52f08a712f14e188723
https://doi.org/10.1109/vlsit.2003.1221107

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Symmetrical 45nm PMOS on [110] substrate with excellent S/D extension distribution and mobility enhancement

Autor: M.F. Lu, S.W. Sun, W.J. Chen, A. Kuo, Y.S. Hsieh, C.H. Hsu, D.F. Chen, W.S. Liao, D. Chen, H.S. Lin, S. Huang-Lu, W.T. Shiau, K.Y. Liao, H. Tang, J.R. Hwang, Y.C. Liu, J.J. Shen, J.H. Ho, W.M. Lin

Publikováno v: Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

For the first time, 45 nm PMOS devices on the only 4-fold symmetry zone of [110] surface substrates were demonstrated with excellent diffusion control in the S/D extension region. A 30% drive current enhancement was observed compared to devices on co

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::89f9cb59b66fe0fb75e3e85c8f7303f0
https://doi.org/10.1109/vlsit.2004.1345410

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CoSi/sub 2/ with low diode leakage and low sheet resistance at 0.065 μm gate length

Autor: H.L. Tsai, J.A. Kittl, Qi-Zhong Hong, S. Krishnan, W.T. Shiau, C.P. Chao, Ih-Chin Chen, R.H. Havemann, H. Yang

Publikováno v: International Electron Devices Meeting. IEDM Technical Digest.

This paper presents a comprehensive study of four diode leakage reduction methods, i.e. pre-metal deposition sputter clean, pre-metal deposition amorphization implant, high temperature silicidation, and high temperature metal deposition, for Co salic

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a7c96df61affd7924c3ec0da95f06018
https://doi.org/10.1109/iedm.1997.649475

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