Zobrazeno 1 - 10
of 31
pro vyhledávání: '"W.S. Lindenberger"'
Autor:
W.S. Lindenberger, Steven James Hillenius, H.-I. Cong, George K. Celler, R.L. Field, T. T. Sheng, L.E. Trimble, A. Kamgar
Publikováno v:
IEEE Transactions on Electron Devices. 39:640-647
CMOS dual-modulus, divide by 128/129, prescaler circuits were built in thin Si films on SIMOX (separation by implantation of oxygen) wafers. They operated at 6.2 GHz, which is 50% faster than control circuits built in bulk Si. Detailed electrical cha
Autor:
A. Kamgar, L. E. Trimble, R.L. Field, W.S. Lindenberger, Steven James Hillenius, H.-I. Cong, George K. Celler, James C. Sturm
Publikováno v:
IEEE SOS/SOI Technology Conference.
Summary form only given. CMOS dual-modulus prescaler circuits built in very thin SIMOX films are discussed. They operate at 6.2 GHz, the highest speed ever reported for a digital CMOS circuit and 50% faster than control circuits built in bulk Si. The
Autor:
M.L. Chen, T.E. Smith, Steven James Hillenius, W.S. Lindenberger, S.J. Wang, L. Manchanda, J.M. Sung, Chih-Yuan Lu
Publikováno v:
International Technical Digest on Electron Devices Meeting.
A device characteristics instability in MOSFETs associated with fluorine incorporation in the p/sup +/-gate fabrication is reported. MOSFETs with BF/sub 2/ or boron-implanted polysilicon gates are fabricated identically except at gate implantation. A
Autor:
George K. Celler, James C. Sturm, A. Kamgar, L.E. Trimble, Steven James Hillenius, R.L. Field, H.-I. Cong, W.S. Lindenberger
Publikováno v:
International Technical Digest on Electron Devices Meeting.
CMOS dual-modulus prescaler circuits were built in very thin SIMOX films. They operate at 6.2 GHz, the highest speed ever reported for a digital CMOS circuit and 50% faster than the control circuits built in bulk Si. The high speed is obtained by tak
Autor:
D.P. Favreau, A. Kornblit, Steven James Hillenius, J.A. Swiderski, M.-L. Chen, W. Juengling, W.S. Lindenberger, T.S. Yang
Publikováno v:
International Technical Digest on Electron Devices.
A nitride-sealed L-shaped Si spacer technique is used to form inverse-T gate sub-half micron N- and P-LDD (lightly doped drain) device structures with self-aligned Ti silicided gate and source-drain. The advantage of the L-shaped Si spacer N-LDD devi
Autor:
W.S. Lindenberger, A.C. Dumbri, L. Noda, K.-H. Lee, W.W. Troutman, Y.-H. Wong, C.-T. Liu, J.M. Drynan, R. Dail, James T. Clemens, M.V. Depaolis, M. Nakamae, Philip W. Diodato
Publikováno v:
Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236).
The desire to enhance memory bandwidth in high performance computing components is overwhelming, and early attempts to combine large memories with high performance logic in a single silicon integrated circuit are numerous. However, existing implement
Autor:
Hem M. Vaidya, Philip W. Diodato, W.S. Lindenberger, W.Y.C. Lai, S. Chaudhry, C.-T. Liu, J.H. O'Neill, A.C. Dumbri, Y.-H. Wong, Glenn B. Alers
Publikováno v:
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).
Embedded DRAM memory cells employing advanced capacitor dielectrics (Ta/sub 2/O/sub 5/) have been designed, fabricated, and measured. Memory cell data retention time is used to compare capacitor characteristics between four Ta/sub 2/O/sub 5/ equipmen
Autor:
W.S. Lindenberger, Kwok K. Ng, Fred N. Preuninger, Chorng Ping Chang, A. Kornblit, Taeho H. Kook
Publikováno v:
SPIE Proceedings.
We have studied the effects of gate etching on the threshold voltage of submicron, N-poly gate CMOS devices through etch processing in selected advanced commercial etchers using a variety of etching chemistries. We found that the threshold voltage of
Publikováno v:
Journal of Applied Physics. 51:3241-3245
Oxidation characteristics of the tantalum disilicide films have been investigated in the temperature range of 900°–1050 °C in dry oxygen and steam ambients. The silicide does not oxidize in dry oxygen and oxidizes in steam at a rate lower than th
Publikováno v:
IEEE Transactions on Electron Devices. 27:1425-1430
The MOS-VLSI parameters and process compatibility of a high-conductivity refractory silicide gate with a sheet resistance of ∼ 2 Ω/□ have been evaluated. The gate metallization typically consisted of 2.5 kA TaSi 2 /2.5 kA poly-Si, which was sint