Zobrazeno 1 - 10
of 65
pro vyhledávání: '"W.R. Daasch"'
Publikováno v:
IEEE Design & Test of Computers. 26:74-82
Today's SoC designs contain many types of circuitry, each with various test types. This article revisits the classic test escape models and highlights their limitations in a test environment with different types of circuits and different test types w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1a419529fa07f3de2530891a571590bd
https://doi.org/10.1109/mdt.2009.118
https://doi.org/10.1109/mdt.2009.118
Publikováno v:
IEEE Design & Test of Computers. 26:64-73
The quantity and complexity of data generated at each test manufacturing step can be daunting. This article, which emerged from a tutorial presented at ITC 2008, explains the application of statistics to help process that data and provides examples o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::af84252ca22a40615009cce315e91aaa
https://doi.org/10.1109/mdt.2009.123
https://doi.org/10.1109/mdt.2009.123
Publikováno v:
IEEE Design & Test of Computers. 23:100-109
The expanded role of test demands a significant change in mind-set of nearly every engineer involved in the screening of semiconductor products. The issues to consider range from DFT and ATE requirements, to the design and optimization of test patter
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d633d8f3e1e44b9c6ab895a1eea0f5f9
https://doi.org/10.1109/mdt.2006.37
https://doi.org/10.1109/mdt.2006.37
Publikováno v:
IEEE Design & Test of Computers. 20:46-53
Structured delay tests have been around for years, but how effectively do they identify defective silicon, even at reduced frequency? How much overkill is associated with their use? The authors present data from industrial circuits aimed at these and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::10ec2388009afa50dacc6f283bcefa79
https://doi.org/10.1109/mdt.2003.1232256
https://doi.org/10.1109/mdt.2003.1232256
Publikováno v:
IEEE Design & Test of Computers. 19:74-81
To screen defective dies, I/sub DDQ/ tests require a reliable estimate of each die's defect-free measurement. The nearest-neighbor residual (NNR) method provides a straightforward, data-driven estimate of test measurements for improved identification
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7736464f86d43ab8d4c3b9d46882a150
https://doi.org/10.1109/mdt.2002.1033795
https://doi.org/10.1109/mdt.2002.1033795
Autor:
S. Narendra, Ali Keshavarzi, Manoj Sachdev, Kaushik Roy, Vivek De, Charles F. Hawkins, James W. Tschanz, W.R. Daasch
Publikováno v:
IEEE Design & Test of Computers. 19:36-43
Barriers to technology scaling, such as leakage and parameter variations, challenge the effectiveness of current-based test techniques. This correlative multiparameter test approach improves current testing sensitivity, exploiting dependencies of tra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d816353c48d63f2aee6957c47265b015
https://doi.org/10.1109/mdt.2002.1033790
https://doi.org/10.1109/mdt.2002.1033790
Publikováno v:
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 49:589-593
As process technologies continue to scale, the effects of temperature can no longer be neglected. High on-chip temperature causes frequency degradation, increases wasteful leakage power, and lowers device reliability. Therefore, managing on-chip temp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b47931b3d919d152e5f6c59f9cd8f6bb
https://doi.org/10.1109/tcsii.2002.806247
https://doi.org/10.1109/tcsii.2002.806247
Publikováno v:
ITC
This paper introduces an adaptive test method to dynamically control test flow and test contents with continuous per die updates of test fail rates. The method employs Bayesian statistics to model a separate fail rate for each test. Test reordering a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::428cfb35c3fc9db0b0118fd71f243c83
https://doi.org/10.1109/test.2011.6139173
https://doi.org/10.1109/test.2011.6139173
Publikováno v:
ITC
This paper presents a method using only the rank of the measurements to separate a part's elevated response to parametric tests from its non-elevated response. The effectiveness of the proposed method is verified on the 130nm ASIC. Good die responses
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::74986fd013d395eaeb7703f3394d0eca
https://doi.org/10.1109/test.2009.5355728
https://doi.org/10.1109/test.2009.5355728
Publikováno v:
DFT
This paper examines fault-tolerant DfT (Design for Test) circuits as an effective approach for improved reliability and lower defective parts per million (DPPM). The paper provides a comprehensive examination of one alternative, quadded gate, inter-l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::35c05d1cc9cc26732d7c2c08a75ce5ec
https://doi.org/10.1109/dft.2008.55
https://doi.org/10.1109/dft.2008.55