Zobrazeno 1 - 10
of 45
pro vyhledávání: '"W. Vanherle"'
Autor:
Amey Mahadev Walke, Anne Vandooren, F. M. Bufler, Nancy Heylen, J. Franco, Bich-Yen Nguyen, Gweltaz Gaudin, Lieve Teugels, Veeresh Deshpande, Boon Teik Chan, Dan Mocuta, Walter Schwarzenbach, T. Zheng, W. Li, Z. Wu, Erik Rosseel, Niamh Waldron, Nadine Collaert, E. Vecchio, Nouredine Rassoul, Romain Ritzenthaler, V. De Heyn, Bertrand Parvais, W. Vanherle, Liesbeth Witters, Iuliana Radu, G. Verbinnen, Lan Peng, Fumihiro Inoue, Andriy Hikavyy, Geert Hellings, Katia Devriendt, G. Jamieson, G. Besnard
Publikováno v:
IEEE Transactions on Electron Devices. 65:5165-5171
3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feat
Autor:
Daire J. Cott, Andreas Schulze, Robert Langer, Geert Eneman, Liesbeth Witters, Bastien Douhard, Hiroaki Arimura, Roger Loo, Nadine Collaert, Dan Mocuta, W. Vanherle, Paola Favia, Jerome Mitard, O. Richard, Geoffrey Pourtois
Publikováno v:
ECS Journal of Solid State Science and Technology. 7:P66-P72
Autor:
B. Parvais, G. Besnard, T. Zheng, Anne Vandooren, W. Li, Erik Rosseel, Julien Ryckaert, Nadine Collaert, Boon Teik Chan, Dan Mocuta, Nancy Heylen, E. Vecchio, Lan Peng, Juergen Boemmels, Liesbeth Witters, Steven Demuynck, Iuliana Radu, A. Khaled, G. Jamieson, Niamh Waldron, Philippe Matagne, Nouredine Rassoul, V. De Heyn, Amey Mahadev Walke, Gweltaz Gaudin, Walter Schwarzenbach, D. Radisic, Z. Wu, Katia Devriendt, Haroen Debruyn, Fumihiro Inoue, Bich-Yen Nguyen, Andriy Hikavyy, W. Vanherle, J. Franco, Lieve Teugels
Publikováno v:
2019 Symposium on VLSI Technology.
3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic V th tuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer trans
Autor:
Liesbeth Witters, Z. Wu, Anne Vandooren, G. Mannaert, Nadine Collaert, E. Vecchio, Lars-Ake Ragnarsson, Romain Ritzenthaler, Niamh Waldron, V. De Heyn, Jerome Mitard, Nouredine Rassoul, Boon Teik Chan, Dan Mocuta, Bertrand Parvais, Veeresh Deshpande, Fumihiro Inoue, Lan Peng, Andriy Hikavyy, G. Jamieson, J. Franco, W. Vanherle, Lieve Teugels, T. Zheng, W. Li, Amey Mahadev Walke, Katia Devriendt, Erik Rosseel, Julien Ryckaert, Nancy Heylen, Steven Demuynck, Geert Hellings, Juergen Boemmels
Publikováno v:
2018 IEEE International Electron Devices Meeting (IEDM).
3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device densit
Autor:
Iuliana Radu, Anne Vandooren, T. Zheng, W. Li, Fumihiro Inoue, Niamh Waldron, J. Franco, Andriy Hikavyy, Liesbeth Witters, Nouredine Rassoul, Lieve Teugels, W. Vanherle, E. Vecchio, Nadine Collaert, G. Verbinnen, Bertrand Parvais, V. De Heyn, G. Besnard, F. M. Bufler, B.-Y. Nguyen, Lan Peng, Boon Teik Chan, Dan Mocuta, W. Schwarzenbach, Katia Devriendt, Romain Ritzenthaler, G. Jamieson, Erik Rosseel, Geert Hellings, G. Gaudin, V. Desphande, Nancy Heylen, Amey Mahadev Walke, Z. Wu
3D sequential integration requires top MOSFETs processed at low thermal budget, which can impair the device reliability. In this work, top junction-less device are fabricated with a maximum processing temperature of 525°C. The devices feature high k
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0ee461fd85f0874b4d632f9267f8b128
https://doi.org/10.1109/vlsit.2018.8510705
https://doi.org/10.1109/vlsit.2018.8510705
Autor:
W. Vanherle, Jordi Soler Penades, Roger Loo, Peter Verheyen, Sanja Radosavljevic, Guy Lepage, Yosuke Shimura, Tinneke Van Opstal, Aditya Malik, Joris Van Campenhout, Goran Z. Mashanovich, Milos Nedeljkovic, Muhammad Muneeb, Gunther Roelkens
Publikováno v:
Procedia Engineering
Silicon-based photonic integrated circuits (PICs) operating in the mid-infrared wavelength range are presented. Firstly, it is shown that the operation of the SOI-based waveguide circuits can be pushed beyond the telecom window till a wavelength of 4
Autor:
Geoffrey Pourtois, Andreas Schulze, Liesbeth Witters, Hiroaki Arimura, Robert Langer, Daire J. Cott, Dan Mocuta, W. Vanherle, Roger Loo, Jerome Mitard, Geert Eneman, Paola Favia, Bastien Douhard, Nadine Collaert, Olivier Richard
Publikováno v:
ECS journal of solid state science and technology
Symposium on Semiconductor Process Integration 10 held during the 232nd, Meeting of the Electrochemical-Society (ECS), OCT 01-05, 2017, National Harbor, MD
SEMICONDUCTOR PROCESS INTEGRATION 10
Symposium on Semiconductor Process Integration 10 held during the 232nd, Meeting of the Electrochemical-Society (ECS), OCT 01-05, 2017, National Harbor, MD
SEMICONDUCTOR PROCESS INTEGRATION 10
The continuous scaling of CMOS devices requires new process developments because of the strong reduction of the allowable thermal budget for device processing. This is especially the case for narrow FinFET structures and vertically stacked MOSFET dev
Autor:
Roger Loo, V. Simons, A. Lesniewska, K. Croes, Guy Lepage, Hongtao Chen, Mikael Detalle, S. Balakrishnan, Philippe Absil, S. Lardenois, Yoojin Ban, J. Van Campenhout, Bradley Snyder, P. De Heyn, Andy Miller, M. Pantouvaki, W. Vanherle, S. A. Srinivasan, Ferenc Fodor, R. Boufadil, N. Golshani, Peter Verheyen, J. De Coster
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM)
2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
BASE-Bielefeld Academic Search Engine
2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
BASE-Bielefeld Academic Search Engine
The next generations of data centers require a scalable optical transceiver technology. In this paper we present a silicon photonics platform supporting single-channel data rates of 50Gb/s and above. Advanced process options include 50GHz GeSi electr
Autor:
Kurt Wostyn, Xiaoqiang Jiang, Lars-Ake Ragnarsson, Jan Willem Maes, E. Chiu, Daire J. Cott, A. Sibaja-Hernandez, Michael Eugene Givens, X. Lu, J. Geypen, Jacopo Franco, Roger Loo, Nadine Collaert, W. Vanherle, Hugo Bender, Dan Mocuta, Jerome Mitard, Fu Tang, Guillaume Boccardi, Hiroaki Arimura, Sonja Sioncke, Qi Xie
Publikováno v:
Web of Science
We demonstrate a Si-passivated Ge nMOS gate stack with Dit of ∼5×1010 cm−2eV−1 around midgap and unnoticeable C-V hysteresis at an operating condition (oxide trap density of ∼1×108 cm−2 at V ov /CET=3.5 MV/cm). Insertion of a 3D-compatibl
Autor:
Ts. Ivanov, D. Lin, Sonja Sioncke, Thierry Conard, J. Ceuppens, W. Vanherle, Aaron Thean, Nadine Collaert, W. Art, Laura Nyns, S. De Gendt, Matty Caymax, Annelies Delabie, Herbert Struyf
Publikováno v:
Microelectronic Engineering. 109:46-49
Si cap passivation on Ge shows low border trap response.The Si cap passivation is also suitable for Ge nMOS applications.Low Dit at Ec can be achieved by tuning the amount of Si at the interface.A dry O3 process can be used to control the amount of S