3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability

Autor: Amey Mahadev Walke, Anne Vandooren, F. M. Bufler, Nancy Heylen, J. Franco, Bich-Yen Nguyen, Gweltaz Gaudin, Lieve Teugels, Veeresh Deshpande, Boon Teik Chan, Dan Mocuta, Walter Schwarzenbach, T. Zheng, W. Li, Z. Wu, Erik Rosseel, Niamh Waldron, Nadine Collaert, E. Vecchio, Nouredine Rassoul, Romain Ritzenthaler, V. De Heyn, Bertrand Parvais, W. Vanherle, Liesbeth Witters, Iuliana Radu, G. Verbinnen, Lan Peng, Fumihiro Inoue, Andriy Hikavyy, Geert Hellings, Katia Devriendt, G. Jamieson, G. Besnard

Publikováno v: IEEE Transactions on Electron Devices. 65:5165-5171

3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feat

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::92b4a10dc727e8fb50bf8a9778c9db9e
https://doi.org/10.1109/ted.2018.2871265

Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications

Autor: B. Parvais, G. Besnard, T. Zheng, Anne Vandooren, W. Li, Erik Rosseel, Julien Ryckaert, Nadine Collaert, Boon Teik Chan, Dan Mocuta, Nancy Heylen, E. Vecchio, Lan Peng, Juergen Boemmels, Liesbeth Witters, Steven Demuynck, Iuliana Radu, A. Khaled, G. Jamieson, Niamh Waldron, Philippe Matagne, Nouredine Rassoul, V. De Heyn, Amey Mahadev Walke, Gweltaz Gaudin, Walter Schwarzenbach, D. Radisic, Z. Wu, Katia Devriendt, Haroen Debruyn, Fumihiro Inoue, Bich-Yen Nguyen, Andriy Hikavyy, W. Vanherle, J. Franco, Lieve Teugels

Publikováno v: 2019 Symposium on VLSI Technology.

3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic V th tuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer trans

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::19cefb6cbd6e3debff3f332f344f1440
https://doi.org/10.23919/vlsit.2019.8776490

Silicon-based Photonic Integrated Circuits for the Mid-infrared

Autor: W. Vanherle, Jordi Soler Penades, Roger Loo, Peter Verheyen, Sanja Radosavljevic, Guy Lepage, Yosuke Shimura, Tinneke Van Opstal, Aditya Malik, Joris Van Campenhout, Goran Z. Mashanovich, Milos Nedeljkovic, Muhammad Muneeb, Gunther Roelkens

Publikováno v: Procedia Engineering

Silicon-based photonic integrated circuits (PICs) operating in the mid-infrared wavelength range are presented. Firstly, it is shown that the operation of the SOI-based waveguide circuits can be pushed beyond the telecom window till a wavelength of 4

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d5927392129d1dae5d0ec33e1d43a947
https://doi.org/10.1016/j.proeng.2015.10.154

Epitaxial CVD growth of ultra-thin Si passivation layers on strained Ge Fin structures

Autor: Geoffrey Pourtois, Andreas Schulze, Liesbeth Witters, Hiroaki Arimura, Robert Langer, Daire J. Cott, Dan Mocuta, W. Vanherle, Roger Loo, Jerome Mitard, Geert Eneman, Paola Favia, Bastien Douhard, Nadine Collaert, Olivier Richard

Publikováno v: ECS journal of solid state science and technology
Symposium on Semiconductor Process Integration 10 held during the 232nd, Meeting of the Electrochemical-Society (ECS), OCT 01-05, 2017, National Harbor, MD
SEMICONDUCTOR PROCESS INTEGRATION 10

The continuous scaling of CMOS devices requires new process developments because of the strong reduction of the allowable thermal budget for device processing. This is especially the case for narrow FinFET structures and vertically stacked MOSFET dev

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c0ebe5da27288242f84d263152153c5b
https://hdl.handle.net/10067/1493260151162165141

Si-passivated Ge nMOS gate stack with low Dit and dipole-induced superior PBTI reliability using 3D-compatible ALD caps and high-pressure anneal

Autor: Kurt Wostyn, Xiaoqiang Jiang, Lars-Ake Ragnarsson, Jan Willem Maes, E. Chiu, Daire J. Cott, A. Sibaja-Hernandez, Michael Eugene Givens, X. Lu, J. Geypen, Jacopo Franco, Roger Loo, Nadine Collaert, W. Vanherle, Hugo Bender, Dan Mocuta, Jerome Mitard, Fu Tang, Guillaume Boccardi, Hiroaki Arimura, Sonja Sioncke, Qi Xie

Publikováno v: Web of Science

We demonstrate a Si-passivated Ge nMOS gate stack with Dit of ∼5×1010 cm−2eV−1 around midgap and unnoticeable C-V hysteresis at an operating condition (oxide trap density of ∼1×108 cm−2 at V ov /CET=3.5 MV/cm). Insertion of a 3D-compatibl

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::91782190d738b9e6dfd3b85b6fe06d00
https://doi.org/10.1109/iedm.2016.7838534