Zobrazeno 1 - 10
of 21
pro vyhledávání: '"W. P. Maszara"'
Publikováno v:
Microelectronic Engineering. 49:245-261
A comprehensive approach based on TCAD and statistical methods has been demonstrated for deep submicron SOI CMOS process optimization and manufacturing sensitivity analysis. Second-order response surface models were fitted to ten device characteristi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7b7018ce61032c36136cf90e7314620d
https://doi.org/10.1016/s0167-9317(99)00445-1
https://doi.org/10.1016/s0167-9317(99)00445-1
Publikováno v:
Microelectronic Engineering. 45:29-37
A computationally efficient and suitable device model has been determined and applied for three-dimensional (3-D) modeling and evaluation of body tied versus floating body SOI MOSFETs. Quarter micron Partially-Depleted (PD) devices have been consider
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::333022d8500815699ed2a021c35f0e16
https://doi.org/10.1016/s0167-9317(98)00258-5
https://doi.org/10.1016/s0167-9317(98)00258-5
Publikováno v:
Journal of The Electrochemical Society. 146:281-285
The quality of thin gate oxides grown on separation‐by‐implantation‐of‐oxygen silicon‐on‐insulator (SIMOX SOI) was investigated. The early‐failure‐rate of gate oxides in optimized SIMOX SOI has been as low as in bulk reference samples
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a4cff07316ed1ce84449c65ac405fd3b
https://doi.org/10.1149/1.1391600
https://doi.org/10.1149/1.1391600
Autor:
M-R. Lin, W. P. Maszara
Publikováno v:
ESSDERC
It took quarter of a century for multi-gate transistor to make it from first demonstration in research to a product — 22nm technology node microprocessor in 2012. FinFETs offer superior performance over incumbent planar devices due to their signifi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::84225f810ce55b892cd129ea1dafc013
https://doi.org/10.1109/essderc.2013.6818808
https://doi.org/10.1109/essderc.2013.6818808
Autor:
W. P. Maszara, M-R. Lin
Publikováno v:
ESSCIRC
It took quarter of a century for multi-gate transistor to make it from first demonstration in research to a product - 22nm technology node microprocessor in 2012. FinFETs offer superior performance over incumbent planar devices due to their significa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::abb4f0f643af632160b1302443410380
https://doi.org/10.1109/esscirc.2013.6649058
https://doi.org/10.1109/esscirc.2013.6649058
Autor:
J.-Y. Jason Lin, Shurong Liang, Suyog Gupta, Arunanshu M. Roy, W. P. Maszara, Yoshio Nishi, Krishna C. Saraswat, Bin Yang
Publikováno v:
2012 International Silicon-Germanium Technology and Device Meeting (ISTDM).
We report a low specific contact resistivity of 5.5 x 10-7 Ωcm2 in nickel germanide (NiGe) contacts on n+ Ge. Data fitting with the contact resistivity model by A.M. Roy et al. (2010) suggests SBH of ~0.44eV for NiGe and ~0.55eV for Al/Ti contacts.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6f1741c76978b723b94cb486349c360a
https://doi.org/10.1109/istdm.2012.6222472
https://doi.org/10.1109/istdm.2012.6222472
Autor:
Farid Nemati, Nihar R. Mohapatra, W. P. Maszara, John J. Wuu, Scott Robins, Rajesh Chopra, V. Gopalakrishnan, Hyun-jin Cho, Kevin J. Yang, Rich Roy, Don R. Weiss, Rajesh Gupta, Joseph John Sundarraj, Sam Nakib
Publikováno v:
2010 International Electron Devices Meeting.
Thyristor Random Access Memory (T-RAM) is an ideal candidate for application as an embedded memory due to its substantially better density vs. performance tradeoff and logic process compatibility [1–3]. T-RAM memory embedded in a 32nm logic process
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dc0e3f3a2b974ba5e36f90d5ff0476ad
https://doi.org/10.1109/iedm.2010.5703345
https://doi.org/10.1109/iedm.2010.5703345
Autor:
W. P. Maszara
Publikováno v:
ChemInform. 22
Various approaches to wafer bonding technology are reviewed. Bonding kinetics are discussed as well as different mechanical and chemical thinning techniques. The structural and electrical qualities of state‐of‐the‐art bonded SOI silicon films a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8c4bf94567a6d0ad6d68b9efe5c2b24d
https://doi.org/10.1002/chin.199110368
https://doi.org/10.1002/chin.199110368
Autor:
W. P. Maszara
Publikováno v:
Journal of Applied Physics. 71:1248-1252
CoSi2 layers produced by implantation of cobalt into silicon at 20 keV with doses 3–6×1016 cm−2 were investigated. Room temperature and 355 °C implants produced continuous layers of silicides with similar electrical properties. The minimum shee
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::edd6542c7f4f6dadb6a80990fcac7dbb
https://doi.org/10.1063/1.351297
https://doi.org/10.1063/1.351297
Autor:
R. vanBentum, E. Pruefer, C. Caillat, W. P. Maszara, N. R. Mohapatra, D. Fisch, Z. Johnson, Z. Chalupa
Publikováno v:
2009 IEEE International SOI Conference.
In this paper, the performance of Zero capacitor RAM (Z-RAM ® ) devices, developed in a 45nm SOI CMOS technology, is compared with both symmetric and asymmetric doping schemes. It is shown that the asymmetrically doped Z-RAM (AD) devices offer much
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b5d681fbed97f9fce6df5410491a8fcc
https://doi.org/10.1109/soi.2009.5318778
https://doi.org/10.1109/soi.2009.5318778