Zobrazeno 1 - 10
of 48
pro vyhledávání: '"W. Kent Fuchs"'
Autor:
Michael Amiridis, Kumble Subbaswamy, E. Gordon Gee, Pradeep K. Khosla, Mark Kennedy, John J. DeGioia, Dennis N. Assanis, Paul K. Kearns, Deborah Wince-Smith, Gene D. Block, C. Michael Cassidy, Steven C. Currall, Adam Weinberg, Michael M. Crow, Farnam Jahanian, Clayton Rose, Kim Wilcox, Mark S. Schlissel, Elizabeth Stroble, Robert A. Brown, Mark P. Becker, James P. Clements, L. A. Leshin, Eric Isaacs, John I. Jenkins, W. Randolph Woodson, Kristina M. Johnson, Gary S. May, Eric J. Barron, Jonathan Alger, Julio Frenk, Jere W. Morehead, Patrick Gallagher, W. Kent Fuchs, Robert J. Zimmer, Elisa Stephens, M. David Rudd, Rebecca M. Blank, Michael R. Lovell, Sylvia M. Burwell, Satish K. Tripathi, Lloyd A. Jacobs, Wendy Wintersteen, Martha Kanter, Luis M. Proenza, Timothy D. Sands, Joan T.A. Gabel, Ruth Watkins, Richard B. Myers, Lee C. Bollinger
Publikováno v:
Science
Colleges and universities are critical components of the U.S. innovation ecosystem. These institutions are called upon to play ever-evolving roles in building talent for a changing workforce; achieving scientific breakthroughs; creating new technolog
Autor:
Janak H. Patel, Srikanth Venkataraman, W. Kent Fuchs, I. Hartanto, Sreejit Chakravarty, Elizabeth M. Rudnick
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 6:471-489
This article describes a diagnostic fault simulator for stuck-at faults in sequential circuits that is both time and space efficient. The simulator represents indistinguishable classes of faults as memory efficient lists. The use of lists reduces the
Autor:
P.G. Ryan, W. Kent Fuchs
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 6:176-180
This paper presents dynamic two stage fault isolation for sequential random logic VLSI circuits, and introduces limited and dynamic fault dictionaries. In the first stage of the dynamic process, a limited fault dictionary identifies candidate faults,
Autor:
Nuno Neves, W. Kent Fuchs
Publikováno v:
Scopus-Elsevier
Mobile computing allows ubiquitous and continuous access to computing resources while the users travel or work at a client’s site. The flexibility introduced by mobile computing brings new challenges to the area of fault tolerance. Failures that we
Publikováno v:
Journal of Parallel and Distributed Computing. 33:1-11
Redundant arrays of distributed disks (RADD) can be used in a distributed computing system or database system to provide recovery in the presence of disk crashes and temporary and permanent failures of single sites. In this paper, we look at the prob
Autor:
W. Kent Fuchs, B. Janssens
Publikováno v:
Journal of Parallel and Distributed Computing. 29:211-218
Distributed shared memory (DSM) implemented on a cluster of workstations is an increasingly attractive platform for executing parallel scientific applications. Checkpointing and rollback techniques can be used in such a system to allow the computatio
Publikováno v:
IEEE Transactions on Computers. 44:1096-1107
Multiple instruction rollback (MIR) is a technique that has been implemented in mainframe computers to provide rapid recovery from transient processor failures. Hardware-based MIR designs eliminate rollback data hazards by providing data redundancy i
Publikováno v:
Software: Practice and Experience. 24:1179-1198
llinois, Urbana-Champaign, 1308 W. Main St., Urbana, I llinois 61801, U.S.A. SUMMARY Previous work on compiler-based multiple instruction retry has utilized a series of compiler transformations, loop protection, node splitting, and loop expansion, to
Publikováno v:
Software: Practice and Experience. 24:871-886
This paper describes a compiler-based approach to efficient checkpointing for process recovery. Our implementation is transparent to both the programmer and the hardware. The compiler-generated sparse potential checkpoint code maintains the desired c
Publikováno v:
IEEE Journal of Solid-State Circuits. 29:770-779
Storage/Logic Arrays (SLA's) represent a structured logic array approach to the design of VLSI sequential logic. Design for concurrent error detection and testability is complicated in these arrays by the presence of embedded memory elements and mult