Zobrazeno 1 - 10
of 16
pro vyhledávání: '"W. Heimsch"'
Publikováno v:
IEEE Journal on Selected Areas in Communications. 12:900-908
The paper presents a possible integrated system concept for a direct sequence spread spectrum CDMA radio access system suitable for third-generation mobile radio. The system has been conceived to take account of such diverse services as low bit rate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a5e7593cc2fa4a4aff462e48a9fe4890
https://doi.org/10.1109/49.298064
https://doi.org/10.1109/49.298064
Publikováno v:
IEEE Journal of Solid-State Circuits. 25:48-54
A 2 K*8-b, ECL 100 K compatible BiCMOS SRAM with 3.8-ns (-4.5 V, 60 degrees ) address access time is described. The precisely controlled bit-line voltage swing (60 mV), a current sensing method, and optimized ECL decoding circuits permit a reliable a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9c7a5eeaafceb9210a271da62cb55ec6
https://doi.org/10.1109/4.50283
https://doi.org/10.1109/4.50283
Publikováno v:
IEEE International Solid-State Circuits Conference.
Merged CMOS/bipolar logic (MCSL) is introduced and applied to a BiCMOS ripple adder. the adder shows bipolar performance without additional circuits for level conversion at the input. In contrast to a pure bipolar solution, the area and power are red
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::956561e9f91bffb2f154e9db1d1b1529
https://doi.org/10.1109/isscc.1989.48199
https://doi.org/10.1109/isscc.1989.48199
Publikováno v:
1991., IEEE International Sympoisum on Circuits and Systems.
A concept for a BiCMOS implementation of a reduced-instruction-set-computer (RISC) microprocessor CPU is proposed. It is based on a CMOS implementation without architectural changes to maintain software compatibility. The circuit paths are analyzed a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fae73bee67bf75b72cd670618c0454fb
https://doi.org/10.1109/iscas.1991.176819
https://doi.org/10.1109/iscas.1991.176819
Autor:
W. Heimsch, R. Krebs
Publikováno v:
Integrierte Digitale Schaltungen MOS/BICMOS ISBN: 9783540544746
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ef14f06136e7de2402d7ec96522b5063
https://doi.org/10.1007/978-3-662-22037-5_4
https://doi.org/10.1007/978-3-662-22037-5_4
Publikováno v:
Le Journal de Physique Colloques. 49:C4-287
In this work the reliability of a BiCMOS NOR Gate is investigated. A design centering program is used to dimension the width of the MOS transistors in order to make the circuit utmost insensible to current efficiency fluctuations caused by process pa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::01e8725d1fb69b43756ff12c6e520c05
https://doi.org/10.1051/jphyscol:1988459
https://doi.org/10.1051/jphyscol:1988459
Publikováno v:
IEEE Journal of Solid-State Circuits. 24:1307-1311
A merged CMOS/bipolar current switch logic (MCSL) is presented. CMOS/ECL level conversion and logical operation are realized simultaneously. This circuit technique allows a supply voltage reduction to 3.3 V. A carry delay time of 150 ps/bit for a 4-b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5105e8af3a09cf0e390ed0af26196278
https://doi.org/10.1109/jssc.1989.572603
https://doi.org/10.1109/jssc.1989.572603
Publikováno v:
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference.
In this work the driveability of CMOS and BICMOS NOR decoders are investigated. An optimization procedure is used to find out the ideal dimension of the transistors in order to get maximum circuit speed. The BICMOS version shows higher speed even at
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9907e2d189e4a4df8b6b72adcd3d9077
https://doi.org/10.1109/esscirc.1988.5468286
https://doi.org/10.1109/esscirc.1988.5468286
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Akademický článek
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