Zobrazeno 1 - 9
of 9
pro vyhledávání: '"W. H. Henkels"'
Publikováno v:
1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199).
Design issues associated with dynamic circuits such as collisions, pulse widening, and noise margins are anticipated to be very sensitive to SOI process and device conditions. Multi-port dynamic register files and latches are important elements in cu
Autor:
W. H. Henkels
Publikováno v:
Journal of Applied Physics. 50:8143-8168
Fundamental design criteria for Josephson nondestructive readout random access memory (NDRO RAM) cells are presented, within the context of an LSI array environment. Emphasis is placed upon principles which are relevant to high performance. The crite
Publikováno v:
IBM Journal of Research and Development. 24:143-154
Design work on components for Josephson computer technology nondestructive read out cache memories has been published previously. In this paper, presenting a design for a 2.5-µm technology, 4 × 1K-bit cache chip with a nominal access time of about
Publikováno v:
Journal of Applied Physics. 58:2379-2388
A detailed optimized design of a 1 K‐bit memory cell array with drivers and reset gates has been carried out based upon a set of projections for achievable tolerances in linewidths, resistances, and Josephson critical currents in a 2.5‐μm techno
Autor:
W. H. Henkels
Publikováno v:
Journal of Applied Physics. 57:855-860
In measurements of superconducting thin‐film penetration depths, the need for a reference penetration depth has been eliminated by a modification of the direct‐coupled SQUID technique. Furthermore, the technique is convenient for accurate measure
Publikováno v:
Journal of Applied Physics. 58:2371-2378
This paper presents an overview of the status of a Josephson cache chip design at IBM in the Fall of 1983. Details of the design, organized as 1 K×4 bits, and employing a 2.5‐μm niobium edge‐junction technology, are found in the subsequent two
Publikováno v:
Journal of Applied Physics. 58:2389-2399
Designs for peripheral and timing circuits for a Josephson cache memory chip, organized as 1 K × 4‐bits, are described. The designs were carried out employing a 2.5‐μm minimum‐linewidth niobium edge‐junction technology, in conjunction with
Autor:
W. H. Henkels
Publikováno v:
Applied Physics Letters. 32:829-831
A technique for accurately measuring small superconductive inductances is presented. The inductance to be measured is inserted into a two‐junction interferometer into which control current is directly injected. The method was used to measure the pe
Publikováno v:
Applied Physics Letters. 29:214-216
The dc I‐V characteristics of superconducting thin‐film Sn‐Au proximity bridges and uniform‐thickness Sn microbridges have been carefully analyzed as a function of the directly measured current‐phase relation (CPR). At sufficiently low dc c