Zobrazeno 1 - 10
of 17
pro vyhledávání: '"W. F. A. Besling"'
Publikováno v:
IEEE Transactions on Advanced Packaging, 33(4), 1072-1079. Institute of Electrical and Electronics Engineers
High-aspect ratio (12.5) through silicon vias (TSV) made in a silicon interposer have been electrically characterized in the direct current (dc) and microwave regimes for 3D interconnect applications. The vias were micro-machined in silicon, insulate
Publikováno v:
Microelectronic Engineering. 82:254-260
Besides cost reduction and yield optimisation, advanced interconnect development is nowadays driven by continuous resistance and capacitance improvement in order to reduce RC-delay with shrinking line dimensions. In order to attain these aggressive g
Publikováno v:
Microelectronic Engineering. 76:167-174
The down scaling of interconnect wiring is facing serious hurdles below 100 nm feature size due to a non-linear resistivity increase with decreasing line width. Moreover, the use of porous low-k dielectrics in combination with narrow line dimensions
Autor:
Marie-Laurence Ignacimouttou, Maxime R. L. Mellier, W. F. A. Besling, Joaquin Torres, Aurelie Humbert
Publikováno v:
Microelectronic Engineering. 76:60-69
''Continuity and Morphology of TaN barriers deposited by Atomic Layer Deposition and Comparison with Physical Vapor Deposition'': After barrier deposition the samples were exposed to a HF solution at various concentrations and various exposure times
Publikováno v:
The Review of scientific instruments. 85(1)
The design of a fluidized bed atomic layer deposition (ALD) reactor is described in detail. The reactor consists of three parts that have all been placed in one protective cabinet: precursor dosing, reactor, and residual gas treatment section. In the
Autor:
Sandrine Lhostis, Canan Baristiran Kaynak, Guenther Ruhl, E Erik Langereis, P. Baumann, Suvi Haukka, Aomar Halimaou, Mindaugas Lukosius, A. Roest, Fred Roozeboom, Benoît Riou, Wolfgang Lehnert, Tom E. Blomberg, Christian Wenger, Wilhelmus M. M. Kessels, W. F. A. Besling, Andy Zauner, Simon A. Rushworth
Publikováno v:
ECS Journal of Solid State Science and Technology, 3(8), N120-N125. Electrochemical Society, Inc.
Future MIM capacitor generations will require significantly increased specific capacitances by utilization of high-k dielectric materials. In order to achieve high capacitance per chip area, these dielectrics have to be deposited in three-dimensional
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4f4e1fab2ef5736482a51f5bd29bebdb
https://research.tue.nl/nl/publications/8b003621-69a1-40e9-80cc-8be45bf67d39
https://research.tue.nl/nl/publications/8b003621-69a1-40e9-80cc-8be45bf67d39
Publikováno v:
Journal of Applied Physics. 83:544-553
Laser-induced chemical vapor deposition of silicon carbonitride thin films has been investigated using a continuous wave CO2 laser in parallel configuration with the substrate. The reactant gases in this process, hexamethyl disilazane and ammonia, ar
Autor:
V.H. Nguyen, Romano Hoofman, W. F. A. Besling, M. Broekaart, Vincent Arnal, M. Fayolle, L.G. Gosset, Francesca Iacopi
Publikováno v:
Dielectric Films for Advanced Microelectronics
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::af8a3ca1ece2081af6dc83ae5151110d
https://doi.org/10.1002/9780470017944.ch5
https://doi.org/10.1002/9780470017944.ch5
Autor:
C. Maurice, E. Sabouret, H. Bono, Alexis Farcy, M. Guillermet, E. Richard, M. Zaleski, D. Reber, Lucile Broussous, Cindy K. Goldberg, J. Mueller, V. Girault, T. Berger, R. Gonella, E. Ollier, V. Plantier, Vincent Arnal, M. Mellier, P. Brun, Aurelie Humbert, B.G. Sharma, John C. Flake, C. Monget, P. Vannier, Robert Fox, J.P. Jacquemin, A. Schussler, G. Imbert, W. F. A. Besling, O. Hinsinger, S. Maubert
Publikováno v:
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
An enhanced trench first hard mask (TFHM) backend integration architecture has been developed to facilitate straightforward ultra low-k (ULK) material insertion and to enable rapid yield learning at the 65nm technology node. Parametric, yield, reliab
Autor:
M. Mellier, J.C. Dupuy, P. Brun, G. Imbert, A. Margain, S. Jullian, Joaquim Torres, R. Gras, S. Chhun, W. F. A. Besling, J. Guillan, T. Van ypre, E. Ollier, L.G. Gosset
Publikováno v:
Proceedings of the IEEE 2006 International Interconnect Technology Conference
Proceedings of the IEEE 2006 International Interconnect Technology Conference, 2006, pp.(IEEE Cat. No. 06TH8862C) (2006) 3
Proceedings of the IEEE 2006 International Interconnect Technology Conference, 2006, pp.(IEEE Cat. No. 06TH8862C) (2006) 3
A hybrid CoWP/SiCN Cu passivation was integrated in a three-metal-level interconnect stack at 65 nm technology node using a porous ULK material (K=2.5). 5 and 20 nm thick Pd-free CoWP electroless barriers were evaluated using a standard trench first