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Autor:
Amarú, Luca, Marranghello, Felipe, Testa, Eleonora, Casares, Christopher, Possani, Vinicius, Jiong Luo, Vuillod, Patrick, Mishchenko, Alan, De Micheli, Giovanni
Publikováno v:
DAC: Annual ACM/IEEE Design Automation Conference; 2020, Issue 57, p215-220, 6p
Autor:
Benini, Luca, Vuillod, Patrick
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Oct98, Vol. 17 Issue 10, p948. 19p.
Publikováno v:
Proceedings of the 1997 IEEE/ACM International Conference: Computer-aided Design; 11/ 9/1997, p13-20, 8p
Autor:
Amaru, Luca, Soeken, Mathias, Vuillod, Patrick, Luo, Jiong, Mishchenko, Alan, Gaillardon, Pierre-Emmanuel, Olson, Janet, Brayton, Robert, De Micheli, Giovanni
Publikováno v:
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Given (i) a Boolean function, (ii) a set of arrival times at the inputs, and (iii) a gate library with associated delay values, the exact delay synthesis problem asks for a circuit implementation which minimizes the arrival time at the output(s). The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ea25db4bf1e982ef7451ea406990436e
https://infoscience.epfl.ch/record/233721
https://infoscience.epfl.ch/record/233721
Autor:
Amarù, Luca Gaetano, Vinicius Possani, Testa, Eleonora, Marranghello, Felipe, Casares, Christoper, Luo, Jiong, Vuillod, Patrick, Alan, Mishchenko, De Micheli, Giovanni
In this paper, we develop a new LUT-based optimization flow tailored for the synthesis of ASICs rather than FPGAs. We enhance LUT-mapping to consider the literal/AIG cost of LUT-nodes. We extend traditional Boolean methods to simplify and re-shape LU
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_______185::e29af0562f548a9d5b392fcee974d38e
https://infoscience.epfl.ch/record/290676
https://infoscience.epfl.ch/record/290676
Autor:
Testa, Eleonora, Amarù, Luca Gaetano, Soeken, Mathias, Mishchenko, Alan, Vuillod, Patrick, Luo, Jingshan, Casares, Christopher, Gaillardon, Pierre-Emanuel
With the continuous push to improve Quality of Results (QoR) in EDA, Boolean methods in logic synthesis have been recently drawing the attention of researchers. Boolean methods achieve better QoR than algebraic methods but require higher computationa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_______185::cbabca4187bb8c150345e14a5009881f
https://infoscience.epfl.ch/record/265931
https://infoscience.epfl.ch/record/265931