Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Vlastimil Kote"'
Publikováno v:
IEEE Transactions on Electron Devices. 67:3270-3277
This article introduces an innovative approach that describes the drain–source current improvements of MOS transistors. It is based on the geometrical modification of MOSFET’s channel from a rectangular layout shape (RLS) into a diamond layout sh
Autor:
Vlastimil Kote, Jiri Jakovenko, Patrik Vacula, Miroslav Husak, M. Vacula, D. Barri, S. Privitera
Publikováno v:
Radioengineering, Vol 28, Iss 3, Pp 598-609 (2019)
Radioengineering. 2019 vol. 28, č. 3, s. 598-609. ISSN 1210-2512
Radioengineering. 2019 vol. 28, č. 3, s. 598-609. ISSN 1210-2512
This article describes waffle power MOSFET segmentation and defines its analytic models. Although waffle gate pattern is well-known architecture for effective channel scaling without requirements on process modification, no until today precise model
Publikováno v:
IEEE Transactions on Electron Devices. 66:3718-3725
In the first part of this article, we have proposed an innovative approach to improve the drain current model of the MOSFETs implemented with the diamond layout style (DLS), regarding the longitudinal corner effect (LCE). The proposed model is more a
Publikováno v:
Integration. 63:18-30
A new pre-placement phase of integrated circuits (IC) analog-mixed-signal (AMS) physical design flow, introduced in this paper, automatically sorts electrical devices used in planar IC technologies according to their topological, structural and elect
Autor:
O. Vesely, Patrik Vacula, Jiri Jakovenko, D. Barri, Vlastimil Kote, V. Molata, O. Tlaskal, Miroslav Husak
Publikováno v:
Radioengineering, Vol 27, Iss 3, Pp 796-805 (2018)
Radioengineering. 2018 vol. 27, č. 3, s. 796-805. ISSN 1210-2512
Radioengineering. 2018 vol. 27, č. 3, s. 796-805. ISSN 1210-2512
A true random number generator (TRNG) with time multiplexed metastability-based sources of randomness, presented in this paper, is capable of generating random bit sequences formed from noise present in the electronic circuit. An incorporated time mu
Publikováno v:
Solid-State Electronics. 170:107822
A spatial systematic mismatch, occurring in the integrated circuit manufacturing process, leads to differences in parameters for two or more identical devices. It is widely accepted that placing devices into symmetrical patterns reduces the spatial s
Autor:
Adam Kubacak, Radek Zeleny, Jiri Jakovenko, Vlastimil Kote, Patrik Vacula, Milan Lzicar, Miroslav Husak
Publikováno v:
2016 11th International Conference on Advanced Semiconductor Devices & Microsystems (ASDAM).
During creation of analog layout in IC CAD environment layout engineers spend a lot of time by modifying objects in a database. By applying new control concept and targeting modern control approaches our solution unifies and simplifies control of any
Publikováno v:
DDECS
The aim of this paper is to present the utilization of modern optimization algorithm called Differential Evolution to automatically fit the appropriate Electrostatic discharge (ESD) model to the measured data from a test chip without the need of manu