Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Vivian A. Bartlett"'
Publikováno v:
Integration. 62:341-352
Ultra-low power operation in power-limited portable devices (e.g. cell phone and smartcard) is paramount. Existing conventional CMOS consume high energy. The adiabatic logic technique has the potential of rendering energy efficient operation. In this
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ad6047e72605a5583c9e7f7dc2964303
https://doi.org/10.1016/j.vlsi.2018.04.002
https://doi.org/10.1016/j.vlsi.2018.04.002
The design and functional verification of the 4-phase adiabatic logic implementation take longer due to the complexity of synchronizing the power-clock phases. Additionally, as the adiabatic system scales, the amount of time in debugging errors incre
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e8d4a9e97a8edc9c3b16e3e868c52cbd
https://eprints.soton.ac.uk/453368/
https://eprints.soton.ac.uk/453368/
Existing secure adiabatic logic designs use charge sharing inputs to deliver input independent energy dissipation and suffer from non-adiabatic losses (NAL) during the evaluation phase of the power-clock. However, using additional inputs present the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e2a3776f762d70c34fb0be57619b532c
https://doi.org/10.1016/j.mejo.2018.04.004
https://doi.org/10.1016/j.mejo.2018.04.004
Publikováno v:
ECCTD
We propose novel resettable adiabatic buffers for five adiabatic logic families namely; Efficient Adiabatic Charge Recovery Logic (EACRL), Improved Efficient Charge Recovery Logic (IECRL), Positive Feedback Adiabatic Logic (PFAL), Complementary Pass-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7fddba522ed8193c56d69906f7f54e42
https://doi.org/10.1109/ecctd.2017.8093257
https://doi.org/10.1109/ecctd.2017.8093257
Publikováno v:
PATMOS
The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider the energy efficiency of a 2-step charging strategy based on a single tank-capacitor circuit. We have investigated the impact of various parame
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3ad7a672398b0866fd1491174e07ee0c
https://doi.org/10.1109/patmos.2016.7833684
https://doi.org/10.1109/patmos.2016.7833684
Publikováno v:
2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).
Resettable adiabatic flip-flops are essential in the design of adiabatic counters, thus, a comprehensive study for IECRL, PFAL and EACRL 4-phase quasi-adiabatic logic families have been done in this paper. In addition, a new resettable quasi-adiabati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::84498bf44bcc45148de99477864e34ec
https://doi.org/10.1109/prime.2016.7519498
https://doi.org/10.1109/prime.2016.7519498
Publikováno v:
2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).
The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider stepwise charging strategies (2, 3, 4, 5, 6, 7, and 8-step) based on tank-capacitor circuits, comparing them in terms of their energy recovery
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::638b7e229c0855402d7b537575deefe6
https://doi.org/10.1109/prime.2016.7519499
https://doi.org/10.1109/prime.2016.7519499