Zobrazeno 1 - 10
of 33
pro vyhledávání: '"Vivek Chickermane"'
Autor:
Brian Foutz, Sarthak Singhal, Prateek Kumar Rai, Krishna Chakravadhanula, Vivek Chickermane, Bharath Nandakumar, Sameer Chillarige, Christos Papameletis, Satish Ravichandran
Publikováno v:
2022 IEEE International Test Conference (ITC).
Autor:
Vivek Chickermane, Brian Edward Foutz, Sarthak Singhal, Christos Papameletis, Krishna Chakravadhanula
Publikováno v:
ITC
Test Compression and logic built-in self-test (LBIST) are proven DFT solutions to address the quality and safety requirements of automotive electronics but their high impact to backend physical implementation can be a huge barrier to successful adopt
Publikováno v:
IEEE Design & Test. 37:5-6
The articles in this special section were presented at the 2019 IEEE VLSI Test Symposium (VTS) that was held in Monterey, CA. The 2019 VTS Conference laid particular emphasis on enlarging its scope by soliciting submissions on testing, reliability, a
Publikováno v:
VTS
Multiple defects are prevalent in early stages of yield improvement for a new technology. When a logic diagnosis procedure is applied to a faulty unit that contains a multiple defect, it sometimes produces a large set of candidate faults. Such a set
Autor:
Brian Edward Foutz, Vivek Chickermane, Louis Christopher Milano, Christos Papameletis, Dale Meehl, Paul Alexander Cunningham, David George Scott, Krishna Chakravadhanula, Steev Wilcox
Publikováno v:
ITC
Test Compression ratios are currently stalled at 100–200X. A new 2-dimensional physically-aware sequential Compressor-Decompressor design addresses the severe wiring congestion as well as the test coverage droop and pattern spike at the highest com
Publikováno v:
IEEE Design & Test. 32:40-48
This paper proposes a design-for-test architecture for efficient testing of 3-D ICs. The DfT architecture supports multiple dies, test data compression, and embedded cores. Commercial EDA tools are used to implement the DfT architecture.
Autor:
Erik Jan Marinissen, Vivek Chickermane, Christos Papameletis, Konstantin Shibin, Brion Keller
Publikováno v:
ATS
Inter-die connections in 2.5D-and 3D-stacked ICs require at-speed testing as their dynamic performance is crucial to the performance of the stack as a whole. In order to test at mission-mode speed and benefit from the already existing clock distribut
Autor:
Vivek Chickermane, K. Chakravadhanula
Publikováno v:
IEEE Design & Test of Computers. 26:6-15
Standardized design and test practices enable automation. This article describes a methodology and corresponding tool set that combines automated support for IEEE Std 1500 and test data compression in one. In this article, we also provide some soluti
Autor:
Richard Schoonover, Krishna Chakravadhanula, Brian Edward Foutz, J. Sage, Brion Keller, Vivek Chickermane, A. Garg, T. Snethen, D. Pearl
Publikováno v:
ITC
As chip design sizes continue to increase and they contain multiple instances of large and small cores, there is a need for a chip test architecture that allows efficient chip-level tests to be created while also reducing the memory and CPU time need
Publikováno v:
VTS
Low-power testing has become a need for modern designs due to rapid increasing of power density with further shrinking of feature size into nanoscale designs. In spite of low-power design efforts and low-power ATPG adopted in common test flows, exces