Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Viv A. Bartlett"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 40:1721-1725
Adiabatic logic is an energy-efficient technique, however, the time required in the design, validation, and debugging increases manifold for large-scale adiabatic system designs. In this endeavor, we present a hardware description language (HDL)-base
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b68b564d5c0c2a5e22e61d02c4198264
https://doi.org/10.1109/tcad.2020.3022334
https://doi.org/10.1109/tcad.2020.3022334
Publikováno v:
PATMOS
On the whole existing secure adiabatic logic designs exhibit variations in current peaks and have asymmetric structures. However, asymmetric structure and variations in current peaks make the circuit vulnerable to Power Analysis Attacks (PAA). In thi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2b1c6fbf7457ba4c0a4ab64f1db38094
https://doi.org/10.1109/patmos.2018.8463996
https://doi.org/10.1109/patmos.2018.8463996
Publikováno v:
PATMOS
In comparison to conventional CMOS (non-adiabatic logic), the verification of the functionality and the low energy traits of adiabatic logic techniques are generally performed using transient simulations at the transistor level. However, as the size
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::60d5cad637f551e6909e5c6cf624a09b
https://doi.org/10.1109/patmos.2018.8464140
https://doi.org/10.1109/patmos.2018.8464140
Publikováno v:
PATMOS
In this paper, we propose Without Charge Sharing Quasi Adiabatic Logic (WCS-QuAL) as a countermeasure against Power Analysis Attacks. We evaluate and compare our logic with the recently proposed secure adiabatic logic designs SPGAL and EE-SPFAL at fr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c5fe92b41c46460e5fdb54e197426d15
https://doi.org/10.1109/patmos.2017.8106968
https://doi.org/10.1109/patmos.2017.8106968
Publikováno v:
ECCTD
In this paper, we propose a novel power analysis attack resilient adiabatic logic which, unlike existing secure adiabatic logic designs doesn't require any charge sharing between the output nodes of the gates. The proposed logic also dissipates less
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c1a1ef0bae581fdc04c116cce49e7ac8
https://doi.org/10.1109/ecctd.2017.8093262
https://doi.org/10.1109/ecctd.2017.8093262
Autor:
Eckhard Grass, Viv A. Bartlett
Publikováno v:
VLSI Design, Vol 12, Iss 3, Pp 349-363 (2001)
Strategies for the design of ultra low power multipliers and multiplier-accumulators are reported. These are optimized for asynchronous applications being able to take advantage of data-dependent computation times. Nevertheless, the low power consump
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::542db223194ba88c77688bf216484dc9
https://doaj.org/article/871a6381f0594cc6888d24342967a789
https://doaj.org/article/871a6381f0594cc6888d24342967a789