Clock gating for power optimization in ASIC design cycle theory & practice.

Autor: S, Jairam, Rao, Madhusudan, Srinivas, Jithendra, Vishwanath, Parimala, H, Udayakumar, Rao, Jagdish

Publikováno v: Proceeding of the 13th International Symposium: Low Power Electronics & Design; 8/11/2008, p307-308, 2p