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pro vyhledávání: '"Vishvanath Janjirala"'
Autor:
Hemanth Krishna L., Neeharika M., Vishvanath Janjirala, Sreehari Veeramachaneni, Noor Mahammad S
Publikováno v:
IET Computers & Digital Techniques, Vol 15, Iss 1, Pp 12-19 (2021)
Abstract This paper proposes an efficient approach to design high‐speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage. This proposed 15:4 counter is designed u
Externí odkaz:
https://doaj.org/article/bdef7fe206c14673bb77006988bfdbfd
Autor:
Vishvanath Janjirala, Noor Mahammad S, M Neeharika, L Hemanth Krishna, Sreehari Veeramachaneni
Publikováno v:
IET Computers & Digital Techniques, Vol 15, Iss 1, Pp 12-19 (2021)
This paper proposes an efficient approach to design high‐speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage. This proposed 15:4 counter is designed using a no
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::14db91813e89002484cd365294841346
https://doaj.org/article/bdef7fe206c14673bb77006988bfdbfd
https://doaj.org/article/bdef7fe206c14673bb77006988bfdbfd