Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Vishnu Ravinuthula"'
Autor:
Scott Kaylor, Sidharth Balasubramanian, Robert C. Keller, William J. Bright, Ken Maclean, Jesse Coulon, Vishnu Ravinuthula, Mark Weaver, Bao Nguyen, Ebenezer Dwobeng
Publikováno v:
VLSI Circuits
We show for the first time an 8.9 GS/s RF current-steering DAC, with an on-chip 1∶1 Balun, and an 8-lane 12.5 Gbps JESD204B compliant SerDes, with a measured LTE ACPR >71 dBc in the adjacent 20 MHz band for a 2.9 GHz channel. The DAC has IM3
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7c010190ee91442cb8566f1b125c0e84
https://doi.org/10.1109/vlsic.2016.7573538
https://doi.org/10.1109/vlsic.2016.7573538
Publikováno v:
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).
This paper presents a fully integrated, low power, low noise Phase-Locked Loop (PLL) implementing a temperature compensated class-C dual-core Voltage Controlled Oscillator (VCO) achieving state of the art phase noise performance. The PLL exhibits low
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6c789cdc6a72f0f6b4329c3110a97c56
https://doi.org/10.1109/rfic.2016.7508243
https://doi.org/10.1109/rfic.2016.7508243
Publikováno v:
International Journal of Circuit Theory and Applications. 37:631-659
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d86f2ebf8a08c33534bfef7f99914afb
https://doi.org/10.1002/cta.488
https://doi.org/10.1002/cta.488
Autor:
Clemenz Portmann, Franz Kuhlmann, Hae-Chang Lee, Shahriar Rabii, Giuseppe Surace, Pulkit Khandelwal, Shaun Lytollis, Ben Kerr, Eugenia Cordero Crespo, Dushmantha Rajapaksha, Hugh Mair, Neil Bulman, Patty Huang, Andrew Keith Joy, Arnold Feldman, Joaquim Machado, Scott Morrison, Vishnu Ravinuthula, Casey Morrison, Peter Hearne
Publikováno v:
ISSCC
In networking systems today data rates are increasing beyond 15Gb/s and yet the installed backplanes are made of low cost materials with losses in excess of 30dB at 7.5GHz. Standards, such as IEEE802.3ap-10GBASE-KR and OIF-CEI25G, are specifying SerD
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::10c4c25ee2e5ed016629388d0ff0fb1c
https://doi.org/10.1109/isscc.2011.5746349
https://doi.org/10.1109/isscc.2011.5746349
Autor:
John G. Harris, Vishnu Ravinuthula
Publikováno v:
ISCAS (1)
We describe a set of basic circuit building blocks for computation using an analog temporal step function representation for the inputs and outputs. Methods for computing weighted averages and thresholded differences are described. These techniques h
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::106211fea7222a0cec8bc00505a10515
https://doi.org/10.1109/iscas.2004.1328192
https://doi.org/10.1109/iscas.2004.1328192