Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Viraj Y. Sardesai"'
Autor:
E. Engbrecht, Edward P. Maciejewski, Christopher D. Sheraw, R. Divakaruni, Zhengwen Li, Allen H. Gabor, L. Economikos, Fernando Guarin, N. Zhan, H-K Lee, MaryJane Brodsky, Kenneth J. Stein, Siyuranga O. Koswatta, Y. Yang, Byeong Y. Kim, J. Hong, A. Bryant, Herbert L. Ho, Ruqiang Bao, Nicolas Breil, Babar A. Khan, E. Woodard, W-H. Lee, C-H. Lin, A. Levesque, Kevin McStay, V. Basker, Viraj Y. Sardesai, C. Tran, A. Ogino, Reinaldo A. Vega, C. DeWan, Shreesh Narasimha, J-J. An, Amit Kumar, A. Aiyar, Ravikumar Ramachandran, W. Wang, X. Wang, W. Nicoll, D. Hoyos, A. Friedman, Barry Linder, Yongan Xu, E. Alptekin, Cathryn Christiansen, S. Polvino, Han Wang, Scott R. Stiffler, G. Northrop, S. Saudari, J. Rice, Saraf Iqbal Rashid, Sunfei Fang, Michael V. Aquilino, Z. Ren, B. Kannan, Geng Wang, Noah Zamdmer, T. Kwon, Paul D. Agnello, Hasan M. Nayfeh, S. Jain, Robert R. Robison, M. Hasanuzzaman, J. Cai, L. Lanzerotti, D. Wehelle-Gamage, Basanth Jagannathan, J. Johnson, E. Kaste, Kai Zhao, Huiling Shang, Carl J. Radens, Shariq Siddiqui, Y. Ke, D. Ferrer, Ximeng Guan, D. Conklin, K. Boyd, K. Henson, Siddarth A. Krishnan, Bernard A. Engel, H. Dong, S. Mahajan, Unoh Kwon, Dominic J. Schepis, William Y. Chang, Liyang Song, Brian J. Greene, Chengwen Pei, S.-J. Jeng, Clevenger Leigh Anne H, Vijay Narayanan, C. Zhu, Wai-kin Li, Henry K. Utomo, Wei Liu, Dureseti Chidambarrao
Publikováno v:
2014 IEEE International Electron Devices Meeting.
We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6233530b0b3fd6ddc14276a018716523
https://doi.org/10.1109/iedm.2014.7046977
https://doi.org/10.1109/iedm.2014.7046977
Autor:
R. Divakaruni, O.S. Kwon, J. Yuan, Huiling Shang, V. Varadarajan, Viraj Y. Sardesai, M. Yu, Nivo Rovedo, Jong Ho Yang, Ying Li, Yong Meng Lee, N. Cave, M.P. Belyansky, Victor Chan, M. Eller, Y.K. Jeong, Narasimhulu Kanike
Publikováno v:
IEEE Electron Device Letters. 30:916-918
PMOS degradation with the blanket-stress-memory-technique (SMT) nitride layer on the (100) wafer with ?100? orientation has been observed, and the degradation mechanism is examined. The boron-doping loss from both the PMOS gate and the source/drain r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::96dc47019da4a545a11188ae782aa0d7
https://doi.org/10.1109/led.2009.2025895
https://doi.org/10.1109/led.2009.2025895
Autor:
Z. Ren, Pranita Kulkarni, R. Zhang, Huiming Bu, D.-G. Park, Viraj Y. Sardesai, Sanjay Mehta, Thomas S. Kanarsky, Kangguo Cheng, Yu Zhu, Keith H. Tabakman, J. Cai, Lisa F. Edge, Ali Khakifirooz, S. Kanakasabapathy, J. Koshy, P. Lindo, S. Wu, Bruce B. Doris
Publikováno v:
2011 International Electron Devices Meeting.
In this paper, we present results and discuss issues related to implementation of large scale circuits in extremely thin (ET) SOI CMOS for low power applications. We have demonstrated that we can fabricate low power (LP) CMOS with centered Vts and go
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::10154907d6e4d5abb6e8c114b587399c
https://doi.org/10.1109/iedm.2011.6131560
https://doi.org/10.1109/iedm.2011.6131560