A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems

Autor: Zongjian Chen, Vincent von Kaenel, Jason Kassoff, Fabian Klass, Weichun Ku, Tony Li, Jonathon Lin, Khurram Malik, Anup Mehta, Dan Murray, Eric Shiu, Priya Ananthanarayanan, Chris Shuler, Sribalan Santhanam, Greg Scott, Junji Sugisawa, Toshinari Takayanagi, Honkai John Tam, Pradeep Trivedi, James Wang, Ricky Wen, John Yong, Sukalpa Biswas, Brian Campbell, Hao Chen, Shailendra Desai, Shaishav Desai, Dominic Go, Rajat Goel

Publikováno v: ISSCC

An SoC is presented with dual 2GHz Powertrade cores, coherent crossbar interconnect, 2MB L2 cache, and memory and I/O subsystem. The chip consumes a maximum of 25W of power. The 115mm2 die is implemented in a 65nm 8M process with low-power design tec

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d4d28527a5d5a46ec1de4889bce0cd57
https://doi.org/10.1109/isscc.2007.373609

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A 2GHz, 7W (max) 64b PowerTM Microprocessor Core.

Autor: Murray, D., Burnette, J., Campbell, B., Chung, M., Fernandes, B., Ghosh, S., Goel, R., Hess, G., Hang Huang, Zhibin Huang, Javarappa, N., Kanapathipillai, P., Klass, F., Fang Liu, Mehta, A., Modukuru, Y., Nerurkar, N., Radhakrishnan, A., Santhanam, S., Sugisawa, J.

Publikováno v: 2007 IEEE Custom Integrated Circuits Conference; 2007, p725-728, 4p

A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for Microprocessor Clock Generation.

Autor: von Kaenel, Vincent, Aebischer, Daniel, Piguet, Christian, Dijkstra, Evert

Publikováno v: Phase-Locking in High-Performance Systems; 2003, p383-390, 8p

High-performancf ALPHA microprocessor design.

Autor: Bailey, D.W.

Publikováno v: 1999 International Symposium on VLSI Technology, Systems & Applications Proceedings of Technical Papers (Cat No99TH8453); 1999, p96-99, 4p