Zobrazeno 1 - 10
of 21
pro vyhledávání: '"Ville Lappalainen"'
Publikováno v:
Microprocessors and Microsystems. 29:155-167
A still image encoder implementation is presented for a multi-DSP system called PARNEU, which has previously been developed for neural network and signal processing applications. The core of the implementation is based on experimental mappings of dis
Publikováno v:
IEEE Transactions on Circuits and Systems for Video Technology. 15:716-725
Multifunctional architecture for video and image processing (MAVIP) to be used in multimedia systems are proposed. MAVIP is a family of reconfigurable architectures derived from a single high-radix (4, 8, or 16) multiplier structure where: a) the lis
Publikováno v:
Signal Processing: Image Communication. 18:861-877
An experimental comparison of video protection methods targeted for wireless networks is presented. Basic methods are the data partitioning, reversible variable length coding, and macroblock row interleaving as well as macroblock scattering for packe
Publikováno v:
IEEE Transactions on Circuits and Systems for Video Technology. 13:717-725
An analysis of computational complexity is presented for an H.26L video decoder, based on extensive experiments on a general-purpose processor. In addition, platform-independent techniques to optimize an H.26L decoder implementation are given. Compar
Publikováno v:
The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology. 34:239-249
Two optimized implementations of the emerging ITU-T H.26L video encoder are described. The first, medium-optimized version, is implemented in C and the latter, highly optimized version, utilizes both algorithmic and platform-specific optimizations. C
Publikováno v:
IEEE Transactions on Circuits and Systems for Video Technology. 12:660-670
This paper summarizes the results of over 25 research groups or individual researchers that have presented video coding implementations on general-purpose processors with the new single instruction multiple data media instruction set architecture ext
Publikováno v:
Microprocessors and Microsystems. 26:1-15
Implementation of H.263/MPEG4 video encoder is presented for a demanding vehicle remote control system. Required features are CIF-sized images, over 25 fps frame rate and flexibility to realize different coding modes and algorithms. A fully DSP-based
Publikováno v:
Computer Networks. 37:425-445
Third generation mobile networks are currently being deployed and user demand for multimedia applications is increasing. We study the quality of service (QoS) of 3GPP 3G-324M mobile videophones over WCDMA networks, using only circuit switched connect
Publikováno v:
IEEE Transactions on Consumer Electronics. 46:706-716
This paper analyses the performance of the state-of-the-art media ISA (instruction set architecture) extensions in a general-purpose processor, when executing a video encoder based on an affine motion model. In addition to SIMD (single instruction mu
Autor:
Timo Hämäläinen, Ville Lappalainen
Publikováno v:
ITCC
A unified method for optimization of video coding algorithms on general-purpose processors is presented. The method consists of algorithmic, code, compiler, and SIMD (Single Instruction Multiple Data) media Instruction Set Architecture (ISA) optimiza