Zobrazeno 1 - 10
of 48
pro vyhledávání: '"Vikram Iyengar"'
Autor:
Carol L. Boggs, Vikram Iyengar
Age-specific patterns of nectar and pollen use by insect pollinators may reflect behavioral or physiological changes over the insect’s lifespan, and may also influence flower visitation rate. Studying Heliconius charithonia (Lepidoptera: Nymphalida
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8ecde23d2ffcf75aea073f2ddc7d7484
https://doi.org/10.1101/2022.05.19.492749
https://doi.org/10.1101/2022.05.19.492749
Publikováno v:
Performance Research. 26:84-85
Autor:
Vikram Iyengar
Publikováno v:
Information & Communications Technology Law. 23:77-80
The recent United States Supreme Court pronouncement in Maryland v. King that the police may readily take a DNA cheek swab of a suspect after an arrest for a serious offense poses challenging Fourth Amendment questions. Moreover, private DNA database
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31:308-321
Physically-aware N-detect (PAN-detect) test improves defect coverage by exploiting defect locality. This paper presents physically-aware test selection (PATS) to efficiently generate PAN-detect tests for large industrial designs. Compared to traditio
Autor:
Xiaolai He, Nirav Acharya, Argun Yetkin, Arkadiusz Kalinowski, Adam J. Kotrba, Nishit Nagar, Timothy Gardner, Vikram Iyengar
Publikováno v:
SAE International Journal of Commercial Vehicles. 2:222-233
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 17:587-592
Product cost is a key driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of ldquobig-D/small-Ardquo mixed-signal system-on-chip (SoC) designs. Packaging cost has recently emerged as a majo
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 22:635-643
Test access mechanisms (TAMs) are an important component of a system-on-chip (SOC) test architecture. TAM optimization is necessary to minimize the SOC testing time. We present a fast, heuristic technique for TAM optimization and demonstrate its scal
Autor:
Krishnendu Chakrabarty, Vikram Iyengar
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21:1088-1094
Test scheduling is an important problem in system-on-a-chip (SOC) test automation. Efficient test schedules minimize the overall system test application time, avoid test resource conflicts, and limit power dissipation during test mode. In this paper,
Autor:
Krishnendu Chakrabarty, Vikram Iyengar
Publikováno v:
IEEE Transactions on Computers. 51:449-459
System-on-a-chip (SOC) designs present a number of unique testability challenges to system integrators. Test access to embedded cores often requires dedicated test access mechanisms (TAMs). We present an improved approach for designing efficient TAMs
Publikováno v:
ITC
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SoC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set