Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Vikas Narang"'
Publikováno v:
SAE Technical Paper Series.
Publikováno v:
2009 1st Asia Symposium on Quality Electronic Design.
As technology is shrinking to sub 100nm, the sensitivity of circuits towards Process, Temperature, Voltage (PTV) and load variations is limiting circuit performance and yield [1–3]. For example in the specific case of IOs, it is difficult to meet v
Publikováno v:
VLSI Design
Voltage scaling is one of the knobs that is used today to control both static and the active power for SoCs. The SoC core supply voltage is scaled adaptively based on the performance needs. But it is also required to maintain the external electrical
Publikováno v:
ACM Great Lakes Symposium on VLSI
An area-efficient, low power, low voltage mobile double-data rate output driver topology for mobile applications is proposed. The driver with its feedback architecture minimizes the overshoot and undershoots by over 50% as compared to a conventional
Publikováno v:
VLSI Design
This paper targets at reducing the crosstalk noise closure time by filtering the set of false violations. We propose two approaches to reduce the pessimism in the crosstalk noise analysis. The first approach uses the arrival time windows for glitch p
Publikováno v:
Journal of clinical gastroenterology. 22(1)
Acute segmental enteritis, also called "enteritis necroticans" is characterized by nonocclusive intestinal ischemia in the absence of any precipitating cause. We studied 30 such patients over a 5.5-year period. All patients had acute abdominal sympto