Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Vijayalakshmi Seshachalam"'
Autor:
Eswar Ramanathan, Zhiguo Sun, Vijaya Rana, Vijayalakshmi Seshachalam, Anbu Selvam Km Mahalingam, Chauhan Kripa Nidhan, Joseph F. Shepard, Tingge Xu, Minrui Wang, Mary Claire Silvestre, Yang Bum Lee
Publikováno v:
2019 China Semiconductor Technology International Conference (CSTIC).
In advanced technology nodes, Multi-color back end of line self-aligned via (SAV) integration involves a stack of dielectric and metallic thin films to memorize the pattern transferred from different color lithography masks. We see intermittent so-ca
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::de9b2ad9e98e3877a46e1262eb526a5c
https://doi.org/10.1109/cstic.2019.8755634
https://doi.org/10.1109/cstic.2019.8755634
Publikováno v:
ECS Meeting Abstracts. :867-867
Back End Of Line (BEOL) Low k Inter Layer Dielectric (ILD) films deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD) processes are typically susceptible to mechanical and chemical damages after integration & downstream processes like Et
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::96bf7d1c0472c848802d3c5ac090186f
https://doi.org/10.1149/ma2017-02/14/867
https://doi.org/10.1149/ma2017-02/14/867
Autor:
C. Wang, Shinichiro Kakita, Rudy Ratnadurai Giridharan, Dingyou Zhang, Luke England, A. Selsley, S. Baral, Sarasvathi Thangaraju, G. Kumarapuram, Mohamed A. Rabie, Wonwoo Kim, R. McGowan, Holly Edmundson, Gu Sipeng, Vijayalakshmi Seshachalam
Publikováno v:
25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014).
This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, Through Silicon Vias (TSV), of 3μm top entrant critical dimension (CD) and 50μm depth. Higher AR TSV integration is explored due to the lower stress
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4d38844234b0657299f27a187e4d85b9
https://doi.org/10.1109/asmc.2014.6846976
https://doi.org/10.1109/asmc.2014.6846976
Autor:
Carlos L. Ygartua, Vijayalakshmi Seshachalam, Ronny Haupt, Alok Vaid, Zhiming Jiang, Michael Lenahan
Publikováno v:
25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014).
In this paper we discuss the impact of these two effects on the film thickness measurement and describe our approach to develop a film stack model and recipe which accounts for the underlying stack as well as Chemical Mechanical Planarization (CMP) v
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5d9966999fd34ee3ad1a66418e9480f9
https://doi.org/10.1109/asmc.2014.6847016
https://doi.org/10.1109/asmc.2014.6847016