Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Vijaya Prakash A M"'
Autor:
Jalaja S, Vijaya Prakash A M
Publikováno v:
AIMS Electronics and Electrical Engineering, Vol 2, Iss 4, Pp 117-130 (2018)
A different method for designing low power retime architecture is presented in this paper. The modified retiming transformation techniques approach to reduce the dynamic power consumption of the digital circuit, without compromising the output result
Externí odkaz:
https://doaj.org/article/ef5933f5275c41809474de995e333043
Publikováno v:
International Journal of Engineering and Advanced Technology. 9:170-176
Tester needs to test software in ECU or implement changes in it and then test software depending on the client’s requirement. To test many real time scenarios, he makes use of ETAS Labcar which helps us to read and write different variables and val
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f93aee688efd0e398e18b51100013ea5
https://doi.org/10.35940/ijeat.f1315.089620
https://doi.org/10.35940/ijeat.f1315.089620
Autor:
Krishna Prasad K, Vijaya Prakash A. M
Publikováno v:
2021 IEEE International Conference on Mobile Networks and Wireless Communications (ICMNWC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fc6ed6827194252bffe14369028dceb2
https://doi.org/10.1109/icmnwc52512.2021.9688435
https://doi.org/10.1109/icmnwc52512.2021.9688435
Tester needs to test software in ECU or implement changes in it and then test software depending on the client’s requirement. To test many real time scenarios, he makes use of ETAS Labcar which helps us to read and write different variables and val
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od______2659::03eee933dbb997e88b78c9fe2b4aba22
https://zenodo.org/record/5529863
https://zenodo.org/record/5529863
Autor:
Vijaya Prakash A M, S. Jalaja
Publikováno v:
AIMS Electronics and Electrical Engineering, Vol 2, Iss 4, Pp 117-130 (2018)
A different method for designing low power retime architecture is presented in this paper. The modified retiming transformation techniques approach to reduce the dynamic power consumption of the digital circuit, without compromising the output result
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f2c85a284adee4a54e9a4f77e241dd5b
https://doi.org/10.3934/electreng.2018.4.117
https://doi.org/10.3934/electreng.2018.4.117
Autor:
Vijaya Prakash A M, S. Jalaja
Publikováno v:
ISVLSI
In digitized world power efficient Successive Approximation Register Analog-to-Digital converter(SAR-ADC) architecture are widely used in most of the electronics applications. It is very compact compared to other ADC architecture. In this proposed pa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0874a6df2e9106f49fee1bb90faa1142
https://doi.org/10.1109/isvlsi.2018.00042
https://doi.org/10.1109/isvlsi.2018.00042
Publikováno v:
IJIREEICE. 3:128-131
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5d3dc4ea900b340934102e880a784b23
https://doi.org/10.17148/ijireeice.2015.31127
https://doi.org/10.17148/ijireeice.2015.31127