Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Vijay Kiran Kalyanam"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:1166-1175
A proactive clock-gating system (PCGS) in a 7-nm Qualcomm® Hexagon™ digital signal processor (DSP) improves performance or energy efficiency by reducing the magnitude of supply voltage ( $V_{\mathrm {DD}}$ ) droops. The PCGS integrates a digital p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fa813a34126971b9bf6b6f9c35491b65
https://doi.org/10.1109/jssc.2020.3043786
https://doi.org/10.1109/jssc.2020.3043786
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:814-823
A Qualcomm® Hexagon™ compute digital signal processor (CDSP) enhances reliability by integrating a current and temperature limiting system to avoid circuit failures from operating at excessive current levels for a sustained duration or from therma
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8076ee5064f475fd89c068c5e0e79cfa
https://doi.org/10.1109/jssc.2020.3047612
https://doi.org/10.1109/jssc.2020.3047612
Publikováno v:
ISSCC
The Hexagon™ compute DSP (CDSP) integrates a master VLIW scalar processor and a slave vector coprocessor to enable high-performance and energy-efficient computing for multimedia, voice, audio, vision, imaging, and machine-learning (ML) applications
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4056805b1ea14c34a674962673152043
https://doi.org/10.1109/isscc42613.2021.9366001
https://doi.org/10.1109/isscc42613.2021.9366001
Publikováno v:
ITC
Precisely controlled power delivery is critical for high performance systems-on-chip. This work describes functional test sequences to induce large dynamic and static supply voltage droops impacting the minimum operating voltage (V MIN ) of the proce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e1f6a003ed637108944b62c91385b212
https://doi.org/10.1109/itc44778.2020.9325271
https://doi.org/10.1109/itc44778.2020.9325271
Publikováno v:
VLSI Circuits
A proactive clock-gating system (PCGS) in a 7nm Qualcomm¯ Hexagon™ digital signal processor (DSP) predicts supply voltage (V DD ) droops based on microarchitectural events and a power-delivery-network (PDN) model and adapts clock frequency (F CLK
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b07df89ce1e28a19e4b3343cdc2ef740
https://doi.org/10.1109/vlsicircuits18222.2020.9162808
https://doi.org/10.1109/vlsicircuits18222.2020.9162808
Publikováno v:
CICC
A randomized pulse-modulation (RPM) circuit controls the instruction-issue rate in a Qualcomm® Hexagon™ compute DSP (CDSP) for adapting performance to limit current and temperature below target thresholds. The current and temperature limiting syst
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2a27dae825112049071408c1c997d043
https://doi.org/10.1109/cicc48029.2020.9075933
https://doi.org/10.1109/cicc48029.2020.9075933
Publikováno v:
ICCD
We describe a methodology to model the low power and voltage behavior of multi-voltage custom memories in processors. These models facilitate early power-aware verification by abstracting the transistor-level representation of the memory to its power
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::99fd5bc4ed831686f5257c949e325cb0
https://doi.org/10.1109/iccd.2015.7357080
https://doi.org/10.1109/iccd.2015.7357080
Publikováno v:
ACM Great Lakes Symposium on VLSI
Accurately estimating critical path delays is extremely important for yield optimization and for path selection in delay testing. It is well known that dynamic effects such ascoupling noise can significantly affect critical path delays. In traditiona
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4819db447c33b7b611165866b66a8ad6
https://doi.org/10.1145/1228784.1228804
https://doi.org/10.1145/1228784.1228804