Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Vidya A. Chhabria"'
Due to the unavailability of routing information in design stages prior to detailed routing (DR), the tasks of timing prediction and optimization pose major challenges. Inaccurate timing prediction wastes design effort, hurts circuit performance, and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::dff07dcba42e0830fa0bcd00ec2dd300
http://arxiv.org/abs/2305.06917
http://arxiv.org/abs/2305.06917
Publikováno v:
2023 24th International Symposium on Quality Electronic Design (ISQED).
Publikováno v:
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD.
Autor:
Vidya A. Chhabria, Ben Keller, Yanqing Zhang, Sandeep Vollala, Sreedhar Pratty, Haoxing Ren, Brucek Khailany
Publikováno v:
2022 ACM/IEEE 4th Workshop on Machine Learning for CAD (MLCAD).
Publikováno v:
Machine Learning Applications in Electronic Design Automation ISBN: 9783031130731
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0f1642e54ebd797e24b27888fcc58ca2
https://doi.org/10.1007/978-3-031-13074-8_5
https://doi.org/10.1007/978-3-031-13074-8_5
Publikováno v:
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).
Publikováno v:
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).
Autor:
Sachin S. Sapatnekar, Brucek Khailany, Vidya A. Chhabria, Ben Keller, Haoxing Ren, Yanqing Zhang
Publikováno v:
DATE
Vectored IR drop analysis is a critical step in chip signoff that checks the power integrity of an on-chip power delivery network. Due to the prohibitive runtimes of dynamic IR drop analysis, the large number of test patterns must be whittled down to
Publikováno v:
DAC
Traditional methodologies for analyzing electromigration (EM) in VLSI circuits first filter immortal wires using Blech's criterion, and then perform detailed EM analysis on the remaining wires. However, Blech's criterion was designed for two-terminal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::30e8c2ad3659b6ea639efdaba2a1a78f
Autor:
Nikhil Patil, Palkesh Jain, Ashwath Prabhu, Vipul Ahuja, Vidya A. Chhabria, Sachin S. Sapatnekar
Publikováno v:
ASP-DAC
Computationally expensive temperature and power grid analyses are required during the design cycle to guide IC design. This paper employs encoder-decoder based generative (EDGe) networks to map these analyses to fast and accurate image-to-image and s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::28608a55bd36324d2bf0ee19e312b30f
http://arxiv.org/abs/2009.09009
http://arxiv.org/abs/2009.09009