Zobrazeno 1 - 10
of 48
pro vyhledávání: '"Victor M. Van Santen"'
Publikováno v:
IEEE Access, Vol 9, Pp 30687-30697 (2021)
Self-Heating Effects (SHE) is known as one of the key reliability challenges in FinFET and beyond. Large timing guard bands are necessary, which we try to reduce. In this work, we propose operating (biasing) processors at Zero-Temperature Coefficient
Externí odkaz:
https://doaj.org/article/8f0366cefdff49739a159823a5f9461a
Autor:
Victor M. van Santen, Jose M. Gata-Romero, Juan Nunez, Rafael Castro-Lopez, Elisenda Roca, Hussam Amrouch
Publikováno v:
2023 IEEE International Reliability Physics Symposium (IRPS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2da0554b2bf62743b53c3bbbb8e4f8a3
https://doi.org/10.1109/irps48203.2023.10117751
https://doi.org/10.1109/irps48203.2023.10117751
Publikováno v:
IEEE Transactions on Computers. 71:947-958
FeFET is a promising technology for non-volatile on-chip memories. It is rapidly attracting an ever-increasing attention from industry. The advantage of FeFETs is full compatibility with the existing CMOS process beside their low power consumption. T
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b76764d3fd6f32daecf21e3140634efc
https://doi.org/10.1109/tc.2021.3066899
https://doi.org/10.1109/tc.2021.3066899
Autor:
Divya Praneetha Ravipati, Rajesh Kedia, Victor M. Van Santen, Jorg Henkel, Preeti Ranjan Panda, Hussam Amrouch
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 30:339-352
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0c977e0fa02dd41b065737a50ebb4028
https://doi.org/10.1109/tvlsi.2021.3123112
https://doi.org/10.1109/tvlsi.2021.3123112
Autor:
Prasad Gholve, Payel Chatterjee, Chaitanya Pasupuleti, Hussam Amrouch, Narendra Gangwar, Shouvik Das, Uma Sharma, Victor M. van Santen, Souvik Mahapatra
Publikováno v:
Solid-State Electronics. 201:108586
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::18b807f6bfe55edf42e8b7955126e334
https://doi.org/10.1016/j.sse.2022.108586
https://doi.org/10.1016/j.sse.2022.108586
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 67:1949-1953
Self-heating effect (SHE) is a major reliability concern in current and upcoming technology nodes due to its ability to increase the channel’s temperature of transistor and leading to degradations in the key electrical characteristics such as carri
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cc63617e4972cae743c93ebf2b3a4b50
https://doi.org/10.1109/tcsii.2019.2959700
https://doi.org/10.1109/tcsii.2019.2959700
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 66:1527-1531
Bias temperature instability (BTI) is a major reliability concern in the current and upcoming technologies. Current mitigation techniques mainly target circuit and system levels through reducing the stimuli that govern BTI. Such mitigation techniques
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::daa22af51f8e1a70db1cd2bc70fcca07
https://doi.org/10.1109/tcsii.2018.2885850
https://doi.org/10.1109/tcsii.2018.2885850
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 66:2671-2684
Variability is one of the major challenges for CMOS in the nano era. Manufacturers test each circuit sample to ensure that samples that do not meet the desired specification are discarded. However, testing is only effective for variability, which is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::73968c014622187792b57f1dbaeb5dc8
https://doi.org/10.1109/tcsi.2019.2898006
https://doi.org/10.1109/tcsi.2019.2898006
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 19:149-158
The design of reliable circuits in current semiconductor technologies requires worst-case estimations of degradation effects during chip signoff. Hence, semiconductor vendors provide worst-case cell delays in the form of slow/slow process corners and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f822a2fbc5f059bb5808bb2a5af0eea0
https://doi.org/10.1109/tdmr.2019.2893017
https://doi.org/10.1109/tdmr.2019.2893017
Autor:
Animesh Basak Chowdhury, Wentian Jin, Benjamin Tan, Victor M. van Santen, Hussam Amrouch, Prashanth Krishnamurthy, Ilia Polian, Sheldon X.-D. Tan, Ramesh Karri, Farshad Khorrami
Publikováno v:
VTS
With technology scaling approaching atomic levels, IC test and diagnosis of complex System-on-Chips (SoCs) become overwhelming challenging. In addition, sustaining the reliability of transistors as well as circuits at such extreme feature sizes, for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::233cb2d36be9374e8232fef108985fb8
https://doi.org/10.1109/vts50974.2021.9441052
https://doi.org/10.1109/vts50974.2021.9441052