Design and simulation of a RISC-V dual-core lockstep for fault tolerant systems

Autor: Viana, Rafael de Figueredo

Publikováno v: Repositório Institucional da UNISINOS (RBDU Repositório Digital da Biblioteca da Unisinos)
Universidade do Vale do Rio dos Sinos (UNISINOS)
instacron:UNISINOS

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Externí odkaz: https://explore.openaire.eu/search/publication?articleId=od______3056::62fc091d1b51b6f266a885db8848c2b9
http://www.repositorio.jesuita.org.br/handle/UNISINOS/9456