PCIeHLS:an OpenCL HLS framework

Autor: Vesper, Malte, Koch, Dirk, Pham, Khoa

Publikováno v: Vesper, M, Koch, D & Pham, K 2017, PCIeHLS : an OpenCL HLS framework . in Proceedings of FPGAs for Software Programmers (FSP 2017) conference . < https://ieeexplore.ieee.org/document/8084547/ >

One of the goals of high level synthesis (HLS) is to make designing hardware accelerators running on FPGAs accessible to developers with a software background (usually implying developers with little foundations in hardware design). While high level

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=od______3818::db62c39f5ef3d8361c3b9cd7e17b256d
https://www.research.manchester.ac.uk/portal/en/publications/pciehls(cbdfdc33-8a5b-4525-b064-5c3ee746f23e).html

A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems.

Autor: Tradowsky, Carsten, Cordero, Enrique, Orsinger, Christoph, Vesper, Malte, Becker, Jürgen

Publikováno v: Applied Reconfigurable Computing (9783319304809); 2016, p343-351, 9p