Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

Autor: Nguyen My Qui, Chang Hong Lin, Poki Chen

Publikováno v: IEEE Access, Vol 8, Pp 172996-173007 (2020)

This study describes the design and implementation of a 256-bit very long instruction word (VLIW) microprocessor based on the new RISC-V instruction set architecture (ISA). Base integer RV32I and extension instruction sets, including RV32M, RV32F, an

Externí odkaz: https://doaj.org/article/d6c8f810c15d4079ba46bf2989c1b51e

Introducing Machine Learning in a Vectorized Digital Signal Processor

Autor: Ridderström, Linnéa

Machine learning is rapidly being integrated into all areas of society, however, that puts a lot of pressure on resource costraint hardware such as embedded systems. The company Ericsson is gradually integrating machine learning based on neural netwo

Externí odkaz: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-337065

CDSP: A Solution for Privacy and Security of Multimedia Information Processing in Industrial Big Data and Internet of Things

Autor: Xu Yang, Yumin Hou, Junping Ma, Hu He

Publikováno v: Sensors, Vol 19, Iss 3, p 556 (2019)

With the widespread nature of wireless internet and internet of things, data have bloomed everywhere. Under the scenario of big data processing, privacy and security concerns become a very important consideration. This work focused on an approach to

Externí odkaz: https://doaj.org/article/d47476ef225345cb9c7ad4630bc44681

CDSP: A Solution for Privacy and Security of Multimedia Information Processing in Industrial Big Data and Internet of Things

Autor: Yumin Hou, Xu Yang, Hu He, Junping Ma

Publikováno v: Sensors (Basel, Switzerland)
Sensors
Volume 19
Issue 3
Sensors, Vol 19, Iss 3, p 556 (2019)

With the widespread nature of wireless internet and internet of things, data have bloomed everywhere. Under the scenario of big data processing, privacy and security concerns become a very important consideration. This work focused on an approach to

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0ce4fefe18080a7eacfb690be0ed6ec3
https://pubmed.ncbi.nlm.nih.gov/30699989

Mécanismes d'optimisation des performances des processeurs VLIW à tolérance de fautes

Autor: Psiakis, Rafail

Publikováno v: Embedded Systems. Université de Rennes 1, 2018. English. ⟨NNT : ⟩
Embedded Systems. Université de Rennes, 2018. English. ⟨NNT : 2018REN1S095⟩
Embedded Systems. Université Rennes 1, 2018. English. ⟨NNT : 2018REN1S095⟩
Embedded Systems. Université de Rennes 1, 2018. English

Embedded processors in critical domains require a combination of reliability, performance and low energy consumption. Very Long Instruction Word (VLIW) processors provide performance improvements through Instruction Level Parallelism (ILP) exploitati

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::0a1f85b95465b2e361c8bd5baa56de0c
https://inria.hal.science/tel-01956233