Zobrazeno 1 - 10
of 33
pro vyhledávání: '"Verena Hein"'
The Improvement of the Life Time Performance Estimation for Interconnect Stacks in Realistic Layouts
Autor:
Kirsten Weide-Zaage, Verena Hein
Publikováno v:
2021 22nd International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE).
The experimental determination of the intrinsic life time of a metallization stack is determined by the used test structures of metal lines and via-metal test structures. The test structure layout is prepared according to the presumption of the failu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::73ab70bd54c279ce040272be8a2ec2de
https://doi.org/10.1109/eurosime52062.2021.9410880
https://doi.org/10.1109/eurosime52062.2021.9410880
Publikováno v:
2019 20th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE).
The reliability of CMOS circuits is influenced by local inhomogeneities in current density, temperature and mechanical stress. Mechanical stress caused by processing and post-processing sources like material mismatch, temperature steps and extrinsic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2a1da945512355efe78ecb77bad34caf
https://doi.org/10.1109/eurosime.2019.8724562
https://doi.org/10.1109/eurosime.2019.8724562
Publikováno v:
Microelectronics Reliability. 64:259-265
The typical via layout in CMOS technology with AlCu-metallizations and tungsten via is cylindrical. Common vias have a size as small as possible in the related process. More challenging application, temperature and mission profiles require higher rob
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f37e46162df802c1bb7b052030441edd
https://doi.org/10.1016/j.microrel.2016.07.136
https://doi.org/10.1016/j.microrel.2016.07.136
Publikováno v:
2018 19th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE).
The layout and design of the on-chip metallization can influence the reliability of products. Thick wide metal tracks are sensitive for failure mechanisms like electromigration (EM), cracking and delamination. The thermal expansion and the volume inc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7b555de337598f053f6b945218266bed
https://doi.org/10.1109/eurosime.2018.8369904
https://doi.org/10.1109/eurosime.2018.8369904
Publikováno v:
Proceeding of Pan Pac 2018
2018 Pan Pacific Microelectronics Symposium (Pan Pacific)
2018 Pan Pacific Microelectronics Symposium (Pan Pacific), Feb 2018, Waimea, United States. pp.1-6
Proceedings of Pan Pacific Microelectronics Symposium 2018
Proceedings of Pan Pacific Microelectronics Symposium 2018, 2018, Hawai, United States
2018 Pan Pacific Microelectronics Symposium (Pan Pacific)
2018 Pan Pacific Microelectronics Symposium (Pan Pacific), Feb 2018, Waimea, United States. pp.1-6
Proceedings of Pan Pacific Microelectronics Symposium 2018
Proceedings of Pan Pacific Microelectronics Symposium 2018, 2018, Hawai, United States
The technology evolution worsens the stress level of microelectronic applications. The shrinking, higher interconnect stacks, the diversity of functions, higher frequencies and power densities lead to higher stress and more interaction of effects. At
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::785a67783ed3f35ca3eaa34554697546
https://hal.archives-ouvertes.fr/hal-02118006
https://hal.archives-ouvertes.fr/hal-02118006
Autor:
Verena Hein
Publikováno v:
2018 Pan Pacific Microelectronics Symposium (Pan Pacific).
The development and research work has always the challenge to act in and with complexity. A complex system/ problem is characterized by some traits. Such systems/ problems have a high number of variables which are coupled. Complex systems are self-dy
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::18cd592328bc90542b7f908829c285ab
https://doi.org/10.23919/panpacific.2018.8318984
https://doi.org/10.23919/panpacific.2018.8318984
Autor:
Kirsten Weide-Zaage, Verena Hein
Publikováno v:
2018 Pan Pacific Microelectronics Symposium (Pan Pacific).
The downscaling in VLSI systems and the use of new materials requires the development of new test structures and in the case of harsh environment conditions the change of the test conditions to higher applied currents and test temperatures. Furthermo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::94e1e5a63883210b2142cd0628f43e59
https://doi.org/10.23919/panpacific.2018.8319008
https://doi.org/10.23919/panpacific.2018.8319008
Publikováno v:
2017 18th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE).
The metal layout design influences the reliability of the metallization in semiconductor products. An optimized design of the interconnect stack can help to reduce the incidence of dielectric and passivation cracking during Joule heating of the metal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2598a16152a7a591e2c2f57ecd89350b
https://doi.org/10.1109/eurosime.2017.7926226
https://doi.org/10.1109/eurosime.2017.7926226
Publikováno v:
2017 IEEE International Reliability Physics Symposium (IRPS).
The use of a thick Copper layer on top of an AlCu-metallization stack instead of a common thick Aluminium layer triggers the need for a change in the reliability characterization, the test structure layouts and reliability test methods. The failure a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dc9d154597afb8447b81fd7abf9492ab
https://doi.org/10.1109/irps.2017.7936377
https://doi.org/10.1109/irps.2017.7936377
Publikováno v:
Microelectronics Reliability. 54:1724-1728
The miniaturization process of CMOS components creates new challenges for the development of integrated circuits. Especially the connections with a tungsten via between two metal layers can be a problem. Changes in geometry can bear on reliability pr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fd3011ed7469bd4d9540ad8489babdc4
https://doi.org/10.1016/j.microrel.2014.07.042
https://doi.org/10.1016/j.microrel.2014.07.042