Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Venky Subramony"'
Autor:
Masazumi Matsunobu, Henk Niesing, Chenxi Lin, Jeff Johnson, Alexander Ypma, Cyrus E. Tabery, Venky Subramony, Yi Zou, Linmiao Zhang, William Susanto, Dag Sonntag, Ravin Somasundaram, Bastani Vahid, Hakki Ergun Cekli, Zakir Ullah, Jelle Nije
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography XXXII.
In addition to lithography process and equipment induced variations, processes like etching, annealing, film deposition and planarization exhibit variations, each having their own intrinsic characteristics and leaving an effect, a ‘fingerprint’,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::408cee4e7a6f3141074b7ffdefb3fe2a
https://doi.org/10.1117/12.2297304
https://doi.org/10.1117/12.2297304
Autor:
Linmiao Zhang, Zakir Ullah, Joel Thomas, Wim Tjibbo Tel, Ravin Somasundaram, Klaus Thul, Kaustuve Bhattacharyya, Cees Lambregts, Ronald Goossens, Emil Schmitt-Weaver, Venky Subramony, Chris de Ruiter, Masazumi Matsunobu
Publikováno v:
SPIE Proceedings.
With photolithography as the fundamental patterning step in the modern nanofabrication process, every wafer within a semiconductor fab will pass through a lithographic apparatus multiple times. With more than 20,000 sensors producing more than 700GB
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a0bb9414af8e947cc93cddb251cb99ea
https://doi.org/10.1117/12.2258039
https://doi.org/10.1117/12.2258039
Process induced Wafer Geometry impact on center and edge lithography performance for sub 2X nm nodes
Autor:
Jaydeep K. Sinha, Michael Johnson, Wei Yeeng Ng, Sathish Veeraraghavan, Stephen Tran, Venky Subramony, Dave Kewley, Michael Chang
Publikováno v:
2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
The change to vertical NAND will make the process complexity increase in traditional steps for example high temperature furnace processing, film deposition using CVD, CMP to planarize the deposited film, film etching, wafer bevel and backside process
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dd7ab79118e44d419cf531bacd9d5de0
https://doi.org/10.1109/asmc.2015.7164417
https://doi.org/10.1109/asmc.2015.7164417
Autor:
Adlai H. Smith, Calvin Chen Chii Wean, Joseph J. Bendik, Yuji Yamaguchi, Venky Subramony, Ranjan Khurana
Publikováno v:
SPIE Proceedings.
The need for lithographic tool advances for reducing feature size, pitch (low k1 processing), and improving overlay stems directly from next generation circuit layout and performance roadmaps 1 . Overlay error or layer-to-layer misalignment tolerance
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::33f45c7c243c8ab32075dbe9de1f2df2
https://doi.org/10.1117/12.674471
https://doi.org/10.1117/12.674471