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pro vyhledávání: '"Venkateswarlu Surisetty"'
Publikováno v:
Proceedings of the International Conference on Soft Computing Systems ISBN: 9788132226697
In this paper, we present a divide by 16 frequency divider (FD) for high frequency and low power phase locked loop (PLL) designs. The FDs have shown efficiency in different parameters. Divide by 16 FDs are proposed with a hybrid model which combined
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::604bf3d0c021dac7fa8fd84247b5df64
https://doi.org/10.1007/978-81-322-2671-0_47
https://doi.org/10.1007/978-81-322-2671-0_47